Elementary network description for neuromorphic systems with plurality of doublets wherein doublet events rules are executed in parallel

ABSTRACT

A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. Neuronal network and methods for operating neuronal networks comprise a plurality of units, where each unit has a memory and a plurality of doublets, each doublet being connected to a pair of the plurality of units. Execution of unit update rules for the plurality of units is order-independent and execution of doublet event rules for the plurality of doublets is order-independent.

This application is related to U.S. patent application Ser. No.13/239,148, filed contemporaneously herewith and entitled “ElementaryNetwork Description For Efficient Link Between Neuronal Models AndNeuromorphic Systems,” U.S. patent application Ser. No. 13/239,155,filed contemporaneously herewith and entitled “Elementary NetworkDescription For Efficient Memory Management In Neuromorphic Systems,”U.S. patent application Ser. No. 13/239,163, filed contemporaneouslyherewith and entitled “Elementary Network Description For EfficientImplementation Of Event-Triggered Plasticity Rules In NeuromorphicSystems,” U.S. patent application Ser. No. 13/239,255, filedcontemporaneously herewith and entitled “Apparatus And Methods ForSynaptic Update In A Pulse-Coded Network,” and to U.S. patentapplication Ser. No. 13/239,259, filed contemporaneously herewith andentitled “Apparatus And Methods For Partial Evaluation Of SynapticUpdates Based On System Events,” each of the foregoing applicationsbeing commonly owned and incorporated herein by reference in itsentirety.

COPYRIGHT

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to parallel distributed computersystems for simulating neuronal networks that perform neuralcomputations, such as visual perception and motor control.

2. Description of Related Art

Most neuronal models and systems consist of networks of simple units,called neurons, which interact with each other and with the externalworld via connections called synapses. The information processing insuch neuronal systems is carried out in parallel.

There are many specialized software tools that help neuroscientists tosimulate models of neural systems. These tools include NEURON, GENESIS,NEST, BRIAN, and many other freely available software tools thatsimulate biologically plausible and anatomically realistic models. Thesetools are designed with the view to make the design of such modelsconvenient for neuroscientists. However, the tools are cumbersome to beused to design optimized software or hardware engines to simulate suchmodels efficiently, especially when real-time performance is required,as in autonomous robotics applications.

In contrast, there are many low-level languages, such as assemblylanguages, LLVM (low-level virtual machine) language, Java Bytecode,chip instruction sets, etc., that are designed for efficient hardwareimplementations on x86, ARM, and other silicon chips. However, suchlanguages are ill appropriate for parallel simulations of neuronalsystems, mostly because the silicon chips are not designed for suchparallel neuronal simulations.

There is obviously a need to have parallel hardware architectures andcorresponding languages that are optimized for parallel execution andsimulation of neuronal models.

SUMMARY OF THE INVENTION

The present invention satisfies the foregoing needs by providing, interalia, apparatus and methods for elementary network description forneuromorphic systems.

Certain embodiments of the invention provide neuronal networks thatcomprise a plurality of units where each unit has a memory updatedaccording to a unit update rule and a plurality of doublets where eachdoublet is connected to a pair of the units and configured to update thememory of a postsynaptic one of the pair of units in response to anevent received from the presynaptic other of the pair of units accordingto a doublet event rule. Execution of unit update rules for theplurality of units is order-independent and execution of doublet eventrules for the plurality of doublets is order-independent. The doubletevent rules are executable in parallel, and wherein the unit updaterules are executable in parallel. For each doublet, the execution of thecorresponding doublet event rule is triggered in response to a change inthe memory of the presynaptic unit and there is a delay betweenoccurrence of changes in the memory of its corresponding presynapticunit and updates to the memory of its corresponding postsynaptic unit.The doublet event rule for each doublet is triggered when itscorresponding presynaptic unit transmits an event to the each doublet.

Certain embodiments of the invention provide methods of implementingneuronal networks by interconnecting a plurality of units using doubletsconfigured to modify a memory of a postsynaptic unit responsive to anevent received from a presynaptic unit and configuring doublet eventrules that determine how the doublets respond to events. Certainembodiments comprise configuring a unit update rule for each unit thatcontrols the response of the each unit to memory updates initiated by adoublet. Execution of the doublet event rules is order-independent andexecution of the unit update rules is order-independent. Configuringdoublet event rules can include configuring each of the doublet eventrules to be executed within a time step having a duration determined bya system clock after receiving an event during the time step. Eachpresynaptic unit may maintain an event condition that controlstransmission of events to a doublet. An after-event unit update rule maybe configured for each presynaptic unit to be executed in associationwith the transmission of the events, where the after-event unit updaterule causes modification of memory of the each presynaptic unit.

Further features of the present invention, its nature and variousadvantages will be more apparent from the accompanying drawings and thefollowing detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram depicting neural simulator according to oneembodiment of the invention

FIG. 2 is a block diagram illustrating one implementation of modeldevelopment workflow according to the invention.

FIG. 3 is a block diagram illustrating one embodiment of END simulationscomprising ENI communications channel according to the invention.

FIG. 4 is a block diagram illustrating one embodiment of ENIcommunications channel of the invention.

FIG. 5 is a block diagram detailing content, formats and expectedbehavior in ENI, according to one embodiment of the invention.

FIG. 6 is a graphical illustration depicting modes of operation of theENI (scheme) according to one embodiment of the invention.

FIG. 7A is a block diagram illustrating one embodiment of a fullysynchronous communication over the ENI channel, according to oneembodiment of the invention.

FIG. 7B a block diagram illustrating one embodiment of the synchronouscommunication of the embodiment of FIG. 7A with a shift (S=1 in bothdirections), according to one embodiment of the invention.

FIG. 8 is a block diagram illustrating a sample communication model withjunctions and synapses with delays, according to one embodiment of theinvention.

FIG. 9 is a block diagram illustrating one embodiment of communicationsmodel comprising ENI channels, according to one embodiment of theinvention.

FIG. 10 is a block diagram illustrating various exemplary of the ENDengine, according to one embodiment of the invention.

FIG. 11 is a block diagram illustrating logical flow of the doubletevent rule according to one embodiment of the invention.

FIG. 12 is a block diagram illustrating one embodiment of thedoublet-event rule implementing Spike-Timing Dependent Plasticity(STDP), according to one embodiment of the invention.

FIG. 13 comprises a table listing possible values of communicationsparameters.

All Figures disclosed herein are ©Copyright 2011 Brain Corporation. Allrights reserved.

DETAILED DESCRIPTION

Embodiments of the present invention will now be described in detailwith reference to the drawings, which are provided as illustrativeexamples so as to enable those skilled in the art to practice theinvention. Notably, the figures and examples below are not meant tolimit the scope of the present invention to a single embodiment, butother embodiments are possible by way of interchange of or combinationwith some or all of the described or illustrated elements. Whereverconvenient, the same reference numbers will be used throughout thedrawings to refer to same or like parts.

Where certain elements of these embodiments can be partially or fullyimplemented using known components, only those portions of such knowncomponents that are necessary for an understanding of the presentinvention will be described, and detailed descriptions of other portionsof such known components will be omitted so as not to obscure theinvention.

In the present specification, an embodiment showing a singular componentshould not be considered limiting; rather, the invention is intended toencompass other embodiments including a plurality of the same component,and vice-versa, unless explicitly stated otherwise herein.

Further, the present invention encompasses present and future knownequivalents to the components referred to herein by way of illustration.

As used herein, the terms “computer”, “computing device”, and“computerized device”, include, but are not limited to, personalcomputers (PCs) and minicomputers, whether desktop, laptop, orotherwise, mainframe computers, workstations, servers, personal digitalassistants (PDAs), handheld computers, embedded computers, programmablelogic device, personal communicators, tablet computers, portablenavigation aids, J2ME equipped devices, cellular telephones, smartphones, personal integrated communication or entertainment devices, orliterally any other device capable of executing a set of instructionsand processing an incoming data signal.

As used herein, the term “computer program” or “software” is meant toinclude any sequence or human or machine cognizable steps which performa function. Such program may be rendered in virtually any programminglanguage or environment including, for example, C/C++, C#, Fortran,COBOL, MATLAB™, PASCAL, Python, assembly language, markup languages(e.g., HTML, SGML, XML, VoXML), and the like, as well as object-orientedenvironments such as the Common Object Request Broker Architecture(CORBA), Java™ (including J2ME, Java Beans, etc.), Binary RuntimeEnvironment (e.g., BREW), and the like.

As used herein, the terms “connection”, “link”, “transmission channel”,“delay line”, “wireless” means a causal link between any two or moreentities (whether physical or logical/virtual), which enablesinformation exchange between the entities.

As used herein, the term “memory” includes any type of integratedcircuit or other storage device adapted for storing digital dataincluding, without limitation, ROM, PROM, EEPROM, DRAM, SDRAM, DDR/2SDRAM, EDO/FPMS, RLDRAM, SRAM, “flash” memory (e.g., NAND/NOR),MEMRISTOR memory, and PSRAM.

As used herein, the terms “microprocessor” and “digital processor” aremeant generally to include all types of digital processing devicesincluding, without limitation, digital signal processors (DSPs), reducedinstruction set computers (RISC), general-purpose (CISC) processors,microprocessors, gate arrays (e.g., FPGAs), PLDs, reconfigurablecomputer fabrics (RCFs), array processors, secure microprocessors, andapplication-specific integrated circuits (ASICs). Such digitalprocessors may be contained on a single unitary IC die, or distributedacross multiple components.

As used herein, the terms “event”, “action potential”, “pulse”, “spike”,“burst of spikes”, and “pulse train” are meant generally to refer to,without limitation, any type of a pulsed signal, e.g., a rapid change insome characteristic of a signal, e.g., amplitude, intensity, phase, orfrequency, from a baseline value to a higher or lower value, followed bya rapid return to the baseline value and may refer to any of a singlespike, a burst of spikes, an electronic pulse, a pulse in voltage, apulse in electrical current, a software representation of a pulse and/orburst of pulses, a software representation of a latency or timing of thepulse, and any other pulse or pulse type associated with a pulsedtransmission system or mechanism. As used herein, the term “spnet”includes the spiking network described in the Izhikevich publication of2006 and titled: “Polychronization: Computation with Spikes.”

Detailed descriptions of the certain embodiments of the invention,including systems, apparatus and methods, are disclosed herein. Althoughcertain aspects of the invention can best be understood in the contextof parallel simulation engine architecture, implemented in software andhardware, which can efficiently simulate large-scale neuronal systems,embodiments of the invention may also be used for implementing an theinstruction set—Elementary Network Description (END) format—that isoptimized for efficient representation of neuronal systems inhardware-independent manner.

For example, certain embodiments may be deployed in a hardware and/orsoftware implementation of a neuromorphic computer system. In one suchimplementation, an image processing system may include a processorembodied in an application specific integrated circuit (“ASIC”), whichcan be adapted or configured for use in an embedded application such asa prosthetic device.

Example: Outline of a Development Environment

Referring now to the example depicted in FIG. 1, one configuration of aneural simulator development environment 100 is shown and described indetail. In this example, network design, connectivity expansion,monitoring and visualization, engine-specific initialization, and engineblocks may comprise software tools while labeled libraries, high leveldescription, debugging tables, low level description and engine-specificdata format blocks may be implemented as data structures in specificformats which are described in more detail herein.

The neural simulator development environment of FIG. 1 allows a user todefine an arbitrary neural system model and to execute the model on anarbitrary computational platform (the engine). Neural simulatordevelopment 100 may comprise a number of software tools (transparentblocks in FIG. 1) that interact with each other via data structuresconfigured in certain formats, and a computational engine 104, which canbe embodied in a single computer, a computer cluster, GPU, or aspecialized hardware. In certain embodiments, the computational engine104 may be a part of computerized control/sensory input processingapparatus and exchanges data with the rest of the apparatus via a pairof arrows 102 in FIG. 1. By way of example, the computational engine 104receives sensory information from the “real world” via the input 102 andsends motor commands to any appropriate actuators (not shown) of thecontrol apparatus via the output 103 enabling the control/processingrespond to the sensory inputs via a set of drivers.

Typically, a user specifies the desired network layout of the neuralsimulator 100 using a GUI network design tool, e.g., similar toMicrosoft Visual Studio™. In one example, the neural simulator employsspecialized libraries, configured to implement various specializedfunctions. Some specific library modules may be, for example, describedbriefly as “retina+thalamus+V1 with 1M neurons”. In another embodiment,the library modules may be described in more detail, providinginitialization of various default parameters (as appropriate) thatdefine, e.g., plasticity, neuronal dynamics, cortical microcircuitry,etc. The GUI network design tool saves the network layout of the neuralsimulator 100 in a “high-level description” format. In one example, theGUI network design tool is configured to modify the libraries 106 inFIG. 1.

The high-level description of the network layout is compiled into alow-level description (Elementary Network Description—END) 108 using thelibraries 106. For example, the high-level description may comprisedescription of cortical areas V1 and V2 (not shown) and requireconnecting them according to an appropriate connectivity rule stored inthe library 106. The compiler allocates neurons, establishes theconnections between the neurons, etc., and saves the network layout 100in a low-level description that is similar to an assembly language. Inone example, the compiler may provide appropriate tables for monitoringand visualization tool during debugging.

The Elementary Network Description (END) representation acts as anintermediary bottleneck (i.e., a link) between simulator tools andhardware platform implementations as illustrated in FIG. 2. The ENDrepresentation provides an abstraction layer that isolates developingenvironment from the underlying hardware. One objective of END is toisolate the step of developing neural network models from hardwaresimulation tools, as illustrated in FIG. 2. The END approach may operateto partition implementation of neural models (such as the model ofFIG. 1) into two steps. At the first step, neuroscientists create neuralmodels of varying complexity using high-level description language andEND representation. At the second step, developers (programmers andhardware engineers) modify and adapt underlying implementation blocks toadapt and optimize model operation for a particular hardware/softwareplatforms, etc. In this architecture, the END format performs the sameservices as LLVM (low-level virtual machine) or Java bytecode; however,the END format can be optimized for parallel representation andexecution of neuronal systems.

The low-level description of the model is converted to theengine-specific binary form suitable for upload to the computationalengine 104, as shown in FIG. 1. The computational engine is capable ofsaving its current state in the same format for subsequent re-uploading.The binary data is used by the monitoring and visualization block 110 ofFIG. 1 during debugging and visualization of computation results andmonitoring of the system. As described above, the computational engineinteracts with the real world via sensors and actuators (connected tothe hardware by drivers) as depicted by the arrows 102 in FIG. 1.

Elementary Network Description

The elementary network description (END) of the network comprises thelowest-level platform-independent model depiction. In oneimplementation, such description is configured similarly to assemblylanguage description, commonly used in computer programming arts.However, while most existing computer assembly language implementationsare processor-dependent, the END description is hardware-agnostic.

The END description may also operate as a platform-independent linkbetween a high-level description and the platform-specificimplementation of the neural model, as illustrated in FIG. 2. In FIG. 2,blocks 210 (Neural simulators 1-3) denote various network developmenttools (such as, NEURON, GENESIS, NEST), while blocks 220 (Hardwareplatform 1-3) denote different hardware implementations (e.g., CPU,multiprocessor computers (workstations, desktop, server, mainframe,ASICs, FPGA, etc) that are used to execute the respective neuralsimulator models.

In one embodiment of the END implementation, input neural simulatormodel data is provided in an XML format (or any other convenientstructured data format) or in a relational database normal form aimed atproviding minimal set of input data that is sufficient to specifyexactly and completely every aspect of neural simulation model,including but not limited to every neuron, dendritic tree, synapse,neuronal and synaptic classes, plasticity rules, neuronal dynamics, etc.This set of input data is configured via multiple relations between theabove items. This set of input data may be configured in a variety ofways: (i) a collection of multiple files each describing a single datastructure, e.g., a neuron; (ii) a single file (that may be compressed);or (iii) hierarchical directory/folder/file structure; or a combinationthereof.

In one example, the fundamental (atomic) computational unit of thenetwork simulation model is a neuron, referred to as a “unit”. Inanother example the unit comprises a neuronal compartment where theunits are linked by junctions to form dendritic trees, which formneurons. In these examples, the synapses comprise connections from oneunit to another, thereby enabling to describe unit (node)interconnections via a connectivity graph. Such graphs do notnecessarily comprise trees connected to trees through synapses comingfrom somas.

In order to obtain operational network description, each unit (e.g.,neuron, compartment) and each synapse is subject to a set of rules thatgovern its dynamics. In one example, some of these rules compriseclock-based rules that apply to neuronal units and junctions, whileother rules are event-based and apply only to synapses.

By way of example, each neuronal unit may be subject to a set of rulesthat describe spike-generation mechanism for that unit, comprising: (i)the condition for firing a spike; and (ii) a set of modifications thatare applied to the unit dynamic state variables after the spike isfired. Similarly, each synapse is subject to spike rules that determinea set of actions performed on the synapse when a pre-synaptic unit firesand a set of actions performed on the synapse when a post-synaptic unitfires.

In one embodiment, the END format is used to generate a C code thatimplements the computational engine (e.g., the engine 104 in FIG. 1). Inthis embodiment, which is referred to herein as END 1.0, the descriptionof rules comprises code strings that are inserted into a C-code templatein order to provide the neuronal model with arbitrary expandablefunctionality, as illustrated by the examples below.

END 1.0 typically implements an object inheritance structure thatcomprises object classes unit_class, junction_class, synaptic_class, andevent rule with possible subclasses. Each such class has instances,i.e., units, junctions, synapses, and rules.

END 1.0 can be configured to separate the data (units, junctions,synapses) from the methods (update and spike rules), thereby enablingthe computational engine (e.g., the linker 112 of the engine 102 inFIG. 1) to implement data⇄methods interconnections. In someimplementations of the computational engine, the computationaloperations are grouped by data (e.g., for every synapse, all of theactions (rules) are executed for that synapse). In other commonly usedimplementations of the computational engine, e.g., useful with GPUhardware, computational operations are grouped by methods (e.g., forevery update rule, outstanding requests for all synapses that aresubject to that update rule are executed). The END can be configured tooperate equally well with any of the above operational groupingconfigurations.

When implementing large-scale models of complex real-life systems suchas, for example, a mammalian visual system, certain data structuresdescribed by the END format may consume the majority (in one example upto 99%) of the network model resources (memory or CPU, or both).Implementation of these data structures, typically referred to as“canonical structures”, greatly benefits from the use of specializedhardware, such as an ASIC or FGPA optimized to simulate such canonicalstructures. Similarly, in some implementations where certain rules andmethods consume majority of CPU processing resources (e.g., take themost time to execute), development of specialized hardware acceleratorsprovides a substantial increased in processing of canonical methods.Different hardware implementations can hard-wire different methods,leading to a diversity of hardware platforms.

One of the goals attained with the END description is to provide theminimal instruction set that is sufficient for describing neuronalmodels of arbitrary complexity. Herein, the following notation is usedin describing the END format: class or type definition type is encasedin angle brackets < . . . >; the fields within the class (or type) areindented, with respect to the class definition, as shown in theDefinition 1 example, below.

Definition 1:

In the above definition, the statement <unit of (unit_class)> denotesdefinition of an instance of the class “unit_class” having fields“unit_id” and “Initialization” as follows:

<unit of (unit_class)>  unit_id  InitializationThis class defines a neuron or a compartment, but in principle, can beany neural unit, that is executed by the model at a predefined modelexecution time step (e.g., 1 ms). The unit is an instantiation of theobject unit_class that specifies the operations performed at each of themodel time steps. The fields of the unit_class are defined as follows:

-   -   unit_id        is a unique label, e.g., a number or a string, that identifies        each unit. Alternatively, the unit_id is a Perl or PHP or RegEx,        or MATLAB expression that specifies a range of valid ids, and        the actual id is assigned during model build by the linker. For        example, ‘exc(1:1000)’ or ‘exc1:exc1000’.    -   Initialization        is a structure containing initial values of the class fields        that are different from the default values in the definition of        the class. All these have to be declared and already initialized        with default values in the unit class.

<unit_class of (unit_class)>  unit_class_id  execution_condition update_rule  event_condition  after_event_rule  initializationprovides a generic definition of a neuronal model class that specifiesneuronal dynamics, allocates neuronal variables, defines spikeprocessing rules, etc. The class <unit_class> is an object (as inobject-oriented programming) that can be derived from another object ofunit_class. The fields of the <unit class> object are defined asfollows:

-   -   unit_class_id        is a unique name of the object class (string), E.g., ‘exc’ or        ‘p23soma’ or ‘p4cmprtmnt3’. These object names are used by the        neuronal model as names of vectors to refer to the units, e.g.,        in background processes or in I/O processes.    -   execution_condition        the condition that is evaluated at every model execution time        step in order to determine whether or not to execute units of        this class, for example: ‘now%10==0’; or ‘DA>0.1’. If the        execution_condition is absent (the field is blank), then        respective unit is executed at every model time step (i.e., the        system clock step cycle). When a class (subclass) is derived        from a base class (superclass), then the derived class execution        condition overrides the base class execution condition.    -   update_rule        defines a code string that will be converted by the linker to        executable code. In one example, the code string comprises a        forward Euler numerical method notation, such as, for example:

  {grave over ( )}x(t+1) = x(t) + tau*(F(x(t)) ). {grave over ( )}I +=g*(E−V); g += tau*(−g)/5; v += tau*( 2*(v+70)*(v+50)−u+I)/20; u +=tau*0.1*(2*(v+70)− u);{grave over ( )}.

In another example, the code string specifies mappingx(t+1)=‘x(t)+tau*(f(x(t))’ or a C-executable code (function orsubroutine) that are performed at each step of model execution. When theclass is derived from a base class, then the object update rule of thesubclass is executed first, followed by the base class rule, therebyallowing for update of certain variable by the subclass rule execution.

-   -   event_condition        defines a logical statement needed to detect spikes. E.g.        ‘v>30’. It is executed every clock cycle (model time step). When        the class is derived from a base class, then the event_condition        of the subclass replaces the event_condition of the base class.    -   after_event_rule        the code that is executed when a spike is detected. E.g.        ‘v=−65;u=u−8;’ For a derived subclass, the subclass after event        rule is executed before the after event rule of the base class.    -   initialization        sets the initial values of all variables and parameters of the        unit. E.g., ‘float v=0; float u=0; float g_AMPA=0;’. Different        unit classes may have a different number of synaptic        conductances and different variable names. The initialization        string parsed by the linker in order to obtain names of all the        variables during build. Derived object classes may add new        variables. For a derived subclass, the initialization of the        base class is executed first, and then this initialization        later, as it may change some of the default parameters. The        initialization may also change the default parameter values        inherited from the base class. By way of example, the        initialization string ‘float g_NMDA=1; g_AMPA=1’ create a new        variable g_NMDA and resets the value of the existing variable        g_AMPA.

Similarly, junctions and synapses can be described using the samemethodology as above.

<junction of (junction_class)>  unit_id1  unit_id2  initializationprovides a generic definition of a neuronal model class that providesconnectivity between pairs of units. The field junction_class refers tothe name of the parent object class, for example, “gap_junction” or“dendritic_tree”. The class fields are as follows:

-   -   unit_id1, unit_id2        specifies the ids of the two connected neuronal units.    -   initialization

Sets the initial values for the parameters and variables. The classjunction_class may be used as the base to define a subclass<junction_class of (junction_class)> and is declared as follows:

<junction_class of (junction_class)>  junction_class_id execution_condition  unit_class_1  unit_class_2  update_rule initializationwhere

-   -   junction_class_id        is a unique identification label that specifies the class that        can be derived from another class.    -   execution_condition        the condition that is evaluated at every model execution time        step in order to determine whether or not to execute units of        this class, for example: ‘now%10==0’; or ‘DA>0.1’. If the        execution_condition is absent (the field is blank), then        respective unit is executed at every model time step. When a        class (subclass) is derived from a base class (superclass), then        the derived class execution condition overrides the base class        execution condition.    -   unit_class_1        the class identifier of the unit_1;    -   unit_class_2        the class identifier of the unit_2; if omitted, the junction is        assumed to be applied to all unit classes.    -   update_rule        defines a code string that will be converted by the linker to        executable code. In one example, the code string comprises a        forward Euler numerical method notation, such as, for example:    -   ‘g_2to1*(V2-V1), g_1to2*(V1-V2)’.

In another example, applicable to Ohmic junctions, one can skip the_class part and just specify the conductances g_2to1 and g_1to2 in the<junction>. When the class is derived from a base class, then the objectupdate_rule of the subclass is executed first, followed by the baseclass rule, thereby allowing for update of certain variable by thesubclass rule execution.

-   -   Initialization        sets the initial values of variables, if any, used to execute        the update_code.

The class synapse is declared as follows:

<synapse of (synaptic_class)>  pre  post  delay  initializationwhere,

pre postare identifiers of the pre-synaptic unit and the post-synaptic unit,respectively.

-   -   delay        specifies the axonal conduction delay value (in simulation time        steps)    -   initialization        sets the initial parameter and variable values. Similarly to the        junction class, synapse class may be derived from a base synapse        class is declared as follows:

<synaptic_class of (synaptic_class)>  synaptic_class_id  initializationwhere,

-   -   synaptic_class_id        is the unique label that specifies the base class, which is used        as a vector identifier in order to refer to individual synapses        in background processes (though the order may be scrambled).        This class can be derived from another class.    -   initialization        sets the initial values of the parameters and variables for each        synapse, e.g., ‘float w=5; float sd=0; float p=0;’. The class        defining a pre-synaptic event rule that accesses synaptic        variables and post_unit variables, is declared as follows:

<presynaptic_event of (event_rule)>  synaptic_class  post_unit_classwhere,

-   -   synaptic_class        denotes the name of the synaptic class to which this plasticity        rule applies. The object event_rule is used to specify actions        performed when the pre-synaptic unit fires. The rules of the        synaptic_class define the short-term plasticity (STP) and        long-term potentiation (LTP) part of STDP rules for a        pre-synaptic neuron (unit).    -   post_unit_class        specifies the class of the post-synaptic unit thereby defining        the domain of the action of the event_rule thereby providing        information that is required by the STDP rule execution (e.g.,        the class to deliver the post-synaptic potential (PSP) and to        access variables such as last_spike). The class        postsynaptic_event is declared as follows:

<postsynaptic_event of (event_rule)>  synaptic_class  post_unit_classwhere,

-   -   synaptic_class        specifies the name of the synaptic class to which this        plasticity rule applies. The object event_rule is used to define        a list of actions that are performed with synaptic variables        when the post-synaptic unit (as referenced with respect to these        synapses) fires, thereby implementing the LTP part of the STDP        plasticity rule that is executed whenever the post-synaptic unit        fires a spike.    -   post_unit_class        specifies the class of the post-synaptic unit thereby defining        an action domain for this rule. In one embodiment, this rule is        configured to accesses synaptic variables only. The event_rule        class may also be derived from a base class as follows:

<event_rule of (event_rule)>  event_rule_id  rule  initializationwhere,

-   -   event_rule_id        is a unique label that specifies the rule class. Generally, the        rule class may be derived from another object class event_rule.    -   Rule        is a string representation of a code that specifies action        performed upon occurrence of an event. By way of example,        delivery of the post-synaptic potential (PSP) may be specified        as:    -   ‘g+=w’ or ‘I+=w’ or ‘g+=g*p’.

Similarly, actions associated with a presynaptic_event may be definedas:

-   -   ‘p*=STP(now-last_active); w−=LTD(now-last_spike);’        while actions associated with a postsynaptic_event may be        defined as:    -   ‘w+=STDP(now-last_active)’        where:    -   “last_active” is the time elapsed since a previous occasion when        the synapse was active; last_spike is the time of the last spike        of the post-synaptic unit, and    -   ‘now’ is the current time.

In addition, the event_rule class may specify tables, e.g., STDP, LTP,or other biologically motivated tables.

-   -   initialization        sets the initial values of the tables as, for example: ‘STDP={ ,        . . . , };’ or ‘STP={ , . . . , };LTD={ . . . }’.

<background_process>  execution_conditionthe condition that is evaluated every simulation time step to determinewhether or not to run the process. E.g., ‘now%10==0’ or ‘DA>0.1’. Ifabsent, then the process is run every time step. The name of theunit_class or synaptic_class whose local variables can be accessed. Thecode below will be run in a loop within the class members with anarbitrary order (possibly in parallel). If absent, it is assumed thatthe process is run once per ‘true’ execution condition, and each unit orsynapse can be accessed using the unit or synaptic class name. E.g., theunit class ‘exc’ contains units exc[i] with possibly unknown order thatdoes not necessarily correspond to the order in which they are listed

-   -   update rule        the code to be executed, e.g. ‘DA*=0.9’ or in synaptic_class        domain ‘w+=DA*sd; sd*=0.995;’ or without domain just ‘exc[rand(        )].I=100;’    -   initialization        initialization of global variables, e.g., ‘float DA=0’.

The time step of the simulation, and other run-time parameters, can bespecified. There are a few global variables that are accessible toeverybody, e.g. “now”—the present time.

Classes that differ by a parameter should be declared as a single classand the parameter values should be specified in the instantiations. Ifthere are only few, say, two different values of the parameter, then itmay make sense to specify two different classes, each having theparameter hard-wired in the equations.

External Interface

External interface of the END framework describes provision of externalsensory input into neuronal network (e.g., the network 100 of FIG. 1)and delivery of outputs (via for example, the pathways 102 of FIG. 1) toexternal robotic apparatus. END external interface comprises two majorlogical blocks: Sensory Input block, and Output and Monitoring block,described in detail below.

Sensory Input

This block defines connection of the external input to various units ofthe network model. By way of example, sensory class for an N-channel(numbered 1 to N) spiking retinal input may be declared as follows:

<unit_class>  unit_class_id = ‘retina’  after_event_rule   // may beempty

The above class declaration informs the input driver and thecomputational engine where the spikes from the retina will go. Thestructure of the input is further defined using the followingdeclaration of N empty units:

<unit>  unit_id = ‘retina(1:N)’

In one example, there are no update rules that are required to beexecuted at every network time step. Hence, the computational enginewill not spend computational resources on these empty units. However,whenever the spikes from the input channels declared as ‘retina’ arrive,the input driver will put the unit index into a spike queue as if itactually fired a spike (this will trigger the after_event_rule executionby the engine, if it is not empty). The synapses from the unit to otherunits will tell the network what to do with spikes. In the case ofretinal input on LGN, the retina units will have 1-3 synapses onto someLGN cells.

If the input channel feeds continuous signals, then the signal willupdate the variable “I” in each unit every millisecond. In this case,one needs to specify the update rule and the event_condition. Of course,the engine will be executing this code every millisecond.

Output and Monitoring:

The output and monitoring block provides an output interface for thenetwork mode. In one implementation, applicable to motor output from themodel, the output block specifies connections between the network unitsand external motor interface or some other actuators. In one example,the motor interface comprises muscle interface. In another example, themotor interface comprises a motor interface configured to control anexternal robotic apparatus. A unit ‘neck_muscles’ comprising anN-channel motor output object for interfacing with, for example, neckmuscles is declared using END framework as follows:

<unit_class>   asunit_class_id = ‘neck_muscles’   initialization =‘float I=0;’

The above declaration informs the output driver which neurons (units) tomonitor for changes in the values of the current I. The respective Nempty unit objects are then created as follows:

<unit>   unit_id = ‘neck_muscles’

During execution of the model, the computational engine ensures that atleast some of the motor neurons (units) neck_muscles have non-zero(e.g., positive) synaptic projections to these neurons, so that wheneverthe motor neurons fire, the variable I within the unit object is set toa positive value. The output driver, therefore, monitors the variable Iat every model time step, and resets it to I=0 if needed. As the motoroutput interface does not require execution of update rules (at eachmodel execution time step), the computational engine spends minimalresources on maintaining the ‘neck_muscles’ units.

In another implementation, applicable to monitoring neural networkexecution, the output block specifies connections between the networkunits and external monitoring interface.

Hardware Accelerations

As described above, certain elements of the neuronal model benefit fromcomputations that are performed by specific hardware blocks (hardwareaccelerators). By way of example, consider a method update_rule of theunit unit_class that consumes a large portion (e.g., 99%) of the enginecomputational resources:

<unit_class>   unit_class_id=‘simple_model’   update_rule =‘v+=(0.04*v+5).*v+140−u+I; u+= a*(b*v−u);’   event_condition = ‘v>30’  after_event_rule = ‘v=−65;u+=d’   initialization= ‘float v=−65; floatu=0; float a=0.1; float b=0.5; float d=8;’

Provided the implementation of the update_rule does not change from unitto unit and/or from one model run to another, then computationaloperations associated with the update_rule can be more efficientlyexecuted by in a specialized hardware accelerator that may beimplemented in, for example, an ASIC, FPGA, or specialized silicon.Within the END framework, a ‘simple_model’ class is used to instruct thecompiler to direct execution of the code, associated with, for example,the update_rule listed above to the appropriate location correspondingto the hardware accelerator interface. To create such mappings,instances of the simple_model class are instantiated as follows:

<unit of (simple_model)>   unit_id=509   initialization ‘a=0.01; d=2’

Such hardware accelerators (simple_model objects) may be used by the ENDas building blocks for constructing more complex objects. By way ofexample, the neuronal model with, for example, one million (1M) ofsimple_model units (neurons) and, for example, one thousand (1K) neuronswith an extra slow neuronal variable, ‘w’ may be declared using classinheritance mechanism as follows:

<unit_class of (simple_model)>   unit_class_id=‘complex_model’  update_rule = ‘w+=0.001*(0.3*v−w); I−=w’   after_even_rule = ‘w+=1’  initialization=‘float w=0’

A processor in the computational engine (e.g., an ARM chip) that isattached to the specialized hardware will typically process 1K units ofthe above type in order to evaluate dynamics of the variable ‘w’ andincorporate it into the value of the variable I. Then the hardwareaccelerator (analog or digital) hardware may execute 1M+1K instances ofthe simple_model without even realizing that some of the instancescorrespond to a more complex model. Ideally, the specialized hardwarewill contain the most commonly used implementations of neuronal models,synaptic dynamics, etc., and users are free to mix and match thesecanonical capabilities or to add to them whatever extra functionality isneeded.

EXAMPLE 1 Spnet

The spnet typically comprises N=Ne+Ni=1000 neurons, where Ne=800excitatory neurons and Ni=200 inhibitory neurons. Each neuron typicallycomprises M=100 synapses per neuron. All excitatory synapses are plastic(STDP), with a random delay ranging between 1 ms and D=20 ms. Theinhibitory->excitatory synapses are non-plastic with a delay of D=1 ms.There are no inh->inh synapses. The low-level END description of themodel is expressed as follows. The first Ne units are populated by Neexcitatory units:

<unit of (exc)>   unit_id = 1:800Next, Ni inhibitory units are records of the class are populated as:

<unit of (inh)>   unit_id = 801:1000The spnet class is then declared as shown in the Listing 1 below:

Listing 1. <unit_class>   unit_class_id=‘QIF2’   update_rule =‘v+=0.5*((0.04*v+5).*v+140−u+I); v+=0.5*((0.04*v+5).*v+140−u+I);’  event_condition = ‘v>30’   after_event_rule = ‘v=−65;’  initialization = ‘float v=−65; float u=0.2*v; float I=0’ <unit_classof (QIF2)>   unit_class_id=‘exc’   update_rule = ‘u+=0.02.*(0.2*v−u);’  after_event_rule = ‘u+=8; last_spike=now’   initialization = ‘intlast_spike=−1000;’ <unit_class of (QIF2)>   unit_class_id=‘inh’  update_rule = ‘u+=0.1.*(0.2*v−u);’   after_event_rule = ‘u+=2;’   Ne*Mrecords of the class (exc->exc) <synapse of (GLU)>   pre = i   // i=1:Ne  post = j  // a random number between 1 and N   delay // a randomnumber between 1 and D   Ni*M records of the class <synapse of (GABA)>  pre = i   // i=Ne+1:N   post = j // a random number between 1 and Ne<synaptic_class>   synaptic_class_id = ‘GLU’   initialization = ‘floatw=6; float sd=0; int last_active=−1000;’   delay=1 // default delay (ifnot specified in the instance ) <synaptic_class>  synaptic_class_id=‘GABA’   delay=1  // the same for all synapses<presynaptic_event of (EPSP_plus_LTD)>   synaptic_class = ‘GLU’  post_unit_class = ‘QIF2’// i.e., exc and inh <presynaptic_event of(Inhibition)>   synaptic_class = ‘GABA’   post_unit_class = ‘QIF2’//i.e., exc and inh <postsynaptic_event of (LTP)>   synaptic_class = ‘GLU’  post_unit_class=‘exc’ <event_rule>   event_rule_id = ‘EPSP_plus_LTD’  rule = ‘I+=w; sd−=LTD(now-last_spike); last_event=now’  initialization = ‘LTD = {array};’   // exponential decay fromLTP_A=1.2 to zero with LTD_tau=20 ms <event_rule>   event_rule_id =‘LTP’   rule = ‘sd+=LTP(now-last_active);’   initialization = ‘LTP ={array};’ <event_rule>   event_rule_id = ‘Inhibition’   rule = ‘I−=5;’  initialization = ‘’ <background_process>   id = ‘Weight_update’;  execution_condition = ‘now%1000==0’   domain = ‘GLU’   update_rule =‘w += 0.01+sd; if (w<0) w=0; if (w>10) w=10; sd *= 0.9’<background_process>   id = ‘randominput’   update_rule =‘exc[int(floor(rand( )/RAND_MAX*N))].v=30;’Binary Data Format and Engine Pseudocode

The low-level description of the model (such shown in Listing 1 above)contains only minimal information that is necessary to uniquely definenetwork architecture. The description shown in Listing 1 may not besuitable for, inter alia, performing model simulations, because it doesnot provide sufficient level of detail, such as, for example, synapseconnections for each unit, the pre-synaptic connections, post-synaptictargets, etc. A linker uses (e.g., the linker 108 in FIG. 1) thelow-level END description and (i) populates all of the links between theunits; (ii) saves the code and the data in binary or some otherlow-level (machine) format so that to facilitate data and code loadingby the computational engine during model simulations. During simulationexecution (runtime) the engine may create save-points (that is savingthe engine execution state comprising for example, registers and memorycontent, program counter, etc.) in the same (or a different) format, soto enable a rapid restart of model execution from any save-point.

In one embodiment, the computational engine comprises a single-processorcomputer. The engine performs a number of computational cycles (stepsthrough the network) in at predetermined time step. In one example, thetime step is set to one millisecond.

In certain embodiments, the computational engine may be implemented on amulti-core processing platform, an array of single/multicore processors,an FPGA, or a programmable logic fabric with one or more embeddedprocessor cores.

Typically, every <_class> instance in the low-level END descriptioncorresponds to a separate loop execution loop. Computations within eachexecution loop/cycle may be performed in parallel in an order that isoptimized for multi-core implementations. Some cycles may also beperformed in parallel with other cycles. Each _code should be“pre-compiled” and included into the appropriate place in the engine.

In order to achieve execution efficiency during model simulations,neuromorphic hardware implementing the computational engine typicallyhas the following features: (i) fast highly specialized processing ofneuronal dynamics and basic synaptic events, such as synaptic release;and (ii) a general purpose processor (e.g., an ARM core) for performingof computational background processes, such as slow synaptic update,turnover, rewiring, short-term plasticity, etc. Such configurationenables fast execution of the basic synaptic processing (that lesslikely requires frequent modifications by the user) for the majority ofsynapses while allowing for implementation of proprietary boutiqueprocessing for a smaller fraction of synapses.

Minimal Instruction Set END Framework

One objective of a “minimal instruction set” embodiment is to provide alow-level description format comprises (i) unit (neuron) definitions,which declare memory allocations but do not contain actions, (ii)junctions, which couple units, but do not allocate memory of their own;and (iii) rules, which link actions with units or junctions. In oneexample, the actions are clock-driven (that is, executed for theappropriate units at every time step of the neuronal mode simulationexecution). In another example, the actions are event-driven, (that is,the actions are triggered by units via, for example, an event_conditiondeclared for the unit class, which informs the simulator on the actionsthat are performed upon the unit firing a spike. Such events (spike),hence, trigger execution of event-based rules that may be applied toother units or junctions.

Within the END framework a synapse can be declared as a unit comprisingmemory configured to store various variables associated with synapsefunctionality, such as synaptic weight, delay, target destination, etc.A synapse can be considered as pre-synaptic machinery that is ready torelease transmitter. As with unit updates, synaptic update rules (e.g.,maintenance ‘w+=sd; sd*=0.9’) may be clock-based or event-based. Thesynaptic action (e.g., release of neurotransmitter) may be triggered bya spike event at the unit corresponding to the pre-synaptic neuron. Therule describing the release can also perform the depression part of theSTDP and any of the short-term plasticity processes. The LTP part ofSTDP may be effected by a separate, other rule that may be triggered bythe unit corresponding to the post-synaptic neuron. A junction specifiesa connection between a synapse and a post-synaptic unit.

The minimal instruction set example of END enables construction of asimple event-based computer that has enough descriptive capacity todefine an arbitrary neural network.

The syntax and structure of the classes and variables of the minimalinstruction set example of END, described below, is similar to the END1.0 format describes supra.

<unit of unit_class>   unit_id   initialization <unit_class (ofunit_class)>   unit_class_id   initialization <junction ofjunction_class>   junction_id   unit_1   unit_2 <junction_class (ofjunction_class)>   junction_class_id   unit_class_1   unit_class_2 <ruleof rule_class>   subject_id

the id of a unit or junction that is subject to this rule

-   -   trigger_id

the id of the unit that triggers the rule for the subject (forevent-based rules). If omitted, this rule is clock-based.

-   -   Delay

The delay with which this rule has to be executed. If omitted, there isno delay

<rule_class (of rule_class)> rule_class_id execution_condition

e.g. ‘now%10==0’. If omitted, then the rule is executed every time step

-   -   subject_class

the class to which this rule can be applied. Notice that subject classcan be a unit or a junction

code event_condition initialization

EXAMPLE 2 Spnet

Listing 2   // First, allocate memory for neurons <unit_class>  unit_class_id = ‘neuron’   initialization = ‘float v=−65; float u=0;float I=0; int last_spike=−1000;’ <unit_class of neuron>   unit_class_id= ‘exc’ <unit_class of neuron>   unit_class_id = ‘inh’ <unit of exc>  unit_id = 1:800 <unit of inh>   unit_id = 1:200   // Now, assigndynamics to neurons (clock-based rule) <rule_class>   rule_class_id =‘QIF’   subject_class = ‘neuron’   code =‘v+=0.5*((0.04*v+5).*v+140−u+I); v+=0.5*((0.04*v+5).*v+140−u+I);’  event_condition = ‘v>30’ <rule_class of QIF>   rule_class_id = ‘RS’  subject_class = ‘exc’   code = ‘u+=0.02.*(0.2*v−u);’ <rule of RS>  subject_id = exc(1:800) <rule_class of QIF>   rule_class_id = ‘FS’  subject_class = ‘inh’   code = ‘u+=0.1.*(0.2*v−u);’ <rule of FS>  subject_id=inh(1:200)   // Specify the after-spike rest (event-basedrule) <rule_class>   rule_class_id = ‘reset’   code = ‘v=−65;last_spike=now;’ <rule_class of reset>   rule_class_id = ‘RS_reset’  subject_class = ‘exc’   code = ‘u+=8;’ <rule of RS_reset>   subject_id= exc(1:800)   trigger_id = exc(1:800) <rule_class of reset>  rule_class_id = ‘FS_reset’   subject_class = ‘inh’   code = ‘u+=2;’<rule of FS_reset>   subject_id = inh(1:200)   trigger_id = inh(1:200)  //specify synapses.   // Inhibitory synapses are not plastic.<rule_class>   rule_class_id = ‘inhibition’   subject_class = ‘neuron’  rule = ‘I−=6’   // 200*100 records of the form below, each specifyingan inh synapse <rule of inhibition>   subject_id = {an exc or inh unit}  trigger_id = {an index of inh unit}   //Excitatory synapses areplastic, so their weights are stored <unit_class>   unit_class_id =‘synapse’   initialization = ‘float w=5; float sd=0; intlast_active=−1000;’ <unit of synapse>   unit_id = 1:80000   //for eachsynapse, specify its target. This is done via junctions <junction_class>  junction_class_id = ‘GLU’   unit_class_1 = ‘synapse’   unit_class_2 =‘neuron’   // Assign the synapses, i.e., create 80000 records of theform <junction of GLU>   junction_id = 1:80000   unit_1 = 1:80000  unit_2 = {random neuron index}   // Specify which pre-synaptic neuronstrigger which synapses <rule_class>   rule_class_id = ‘EPSP_plus_LTD’  subject_class = ‘GLU’   code =‘I+=w;sd−=LTD(now-last_spike);last_active=now;’   initialization =‘LTD={array}’ <rule of EPSP_plus_LTD>   subject_id = 1:80000  trigger_id = exc(rand(800))   delay = rand(20)   // Specify LTP whenpost-unit fires <rule_class>   rule_class_id = ‘LTP’   subject_class =‘synapse’   rule = ‘sd += LTP(now-last_active)’   initialization =‘LTP={array}’ <rule of LTP>   subject_id = 1:80000   trigger_id ={corresponding post-synaptic neuron, though this could in principle beanything else}   //perform the sd-update (maintenance) <rule_class>  rule_class_id = ‘synaptic_maintenance’   subject_class = ‘synapse’  execution_condition = ‘now%1000==0’   code = ‘w += 0.01+sd; if (w<0)w=0; if (w>10) w=10; sd *= 0.9’ <rule of synaptic_maintenance>  subject_id = 1:80000   // Finally, the random thalamic input thatfires a neuron per ms of time step <rule_class>   rule_class_id =‘input’   code = ‘fire({random neuron});’ <rule of input> // noparameters; just need this to instantiate the inputEND 2.0

The END 2.0 format comprises the following features when compared to theEND 1.0 format described, supra.

-   -   No inheritance (no object classes);    -   No background processes (global variables are used instead);    -   No separate pre-synaptic/post-synaptic rules (all are part of        the synaptic type)    -   Each rule may include other rules and code strings, as well as        execution conditions.

<rule>   name   exec_conditionthe condition that is evaluated every step to determine whether or notto execute this rule. This can be a string e.g., ‘now%10==0’ or ‘DA>0.1’or a reference to a rule name (this is useful if the condition needssome global tables). If absent, then the rule applies for everyexecution time step. This condition may access any variable that isdefined in the code below.

-   -   Code        the code string or other rule name that specifies what to do        when the rule occurs. E.g., ‘1+=w’ or        ‘v+=tau*(2*(v+70)*(v+50)−u+I)/20; u+=tau*0.1*(2*(v+70)−u);’. In        addition, the output of the rule can be a logical (true/false)        statement that is used in spike conditions, etc. Multiple rule        names can be provided here; they will be executed in the        provided order    -   init        declares and sets the values of global variables used in this        rule. E.g. ‘STDP={ , . . . , }; DA=0’ or ‘STP={ , . . . , };        LTD={ . . . }’. Any instance variables are defined in unit_type        and synaptic_type; the linker checks that all data types defined        in different unit_types and synaptic_types are consistent with        respect to the rule.

<unit_type>   name   update_rulecode string or rule name that is executed every time step. Multiplerules can be provided here; they will be executed in the orderspecified.

-   -   event_condition

logical statement or rule name needed to detect spikes. E.g. ‘v>30’.Executed every time step

-   -   event_rule

the code or rule name that is executed when a spike is detected. E.g.‘v=−65; u=u−8;’

-   -   Init

declares and sets the initial values of all variables and parametersused in the unit (i.e., instance variables). The linker (compiler)checks that these variables have consistent data types among all unittypes that use the same rules, for example, ‘analog v=0; analogg_AMPA=0;’

<unit of unit_type> unit_id init

sets the parameter and variable values that are different from thedefault values in the definition of the type. All these have to bedeclared and already initialized with default values in the definitionsof unit_type

<junction_type> name update_rule init <junction of junction_type> unit_1unit_2 init <synaptic_type> type presynaptic_event_rulethe code or rule name that is triggered when the pre-synaptic neuronfires. This takes care of LTP and PSP

-   -   postsynaptic_event_rule        the code or rule name triggered by firing of the post-synaptic        unit. This takes care of the LTD part of STDP    -   update_rule

Code string or rule name that is executed every time step (hopefully, ithas execution_condition and is hence executed rarely). Multiple rulescan be provided here; they will be executed in the order specified. Thisis needed for synaptic maintenance, in lieu of background processes.

<synapse of synaptic_type> pre post delay init <global_variable>update_rule

Rule name that initializes global variables and executes the code thatupdates them. The code may have access to specific instances of units,junctions, or synapses. In the simplest case, the rule can be just anassignment of the value of the global variable based on a value of aninstance.

Notice that instance variables are used in <rules> but they are definedin <unit_type>, <junction_type>, and <synaptic_type>. It is assumed thatall declaration of instance variables are consistent with all the rules.There may be two problems:

Situations where a variable is used in a rule but is not defined inunit_type or junction_type or synaptic_type are handled as follows:

-   -   The linker may generate an error    -   The linker uses a default type of the variable, e.g., “analog”    -   The linker is instructed to look at other usage of the rule and        if the variable is defined somewhere, it extends its definition.        In certain embodiments, a variable can be defined differently in        two or more unit_types that use the same rule. Again, there are        multiple possible solutions to this:    -   The linker generates an error    -   The linker converts one of the definitions to the other one. For        example, there can be a partially ordered set of definitions,        e.g., int8<int16<int32<int64<analog, so that two definitions are        transformed to the common one    -   The linker splits the rule into two rules, rule_a and rule_b,        that act on different types of variables

EXAMPLE 2 Global Variables

<rule> name = ‘DA_update’ code = ‘DA = exc[3].v + inh[1].u’ init =‘analog DA = 0’ <global_variable> update_rule = ‘DA_update’

EXAMPLE 3 Spnet

The standard spnet network has N=1000 neurons; among them are Ne=800excitatory neurons and Ni=200 inhibitory neurons, with M=100 synapsesper neuron. All excitatory synapses are plastic (STDP), with randomdelay between 1 and D=20 ms. The inhibitory->excitatory synapses arenon-plastic with delay D=1 ms. There are no inh->inh synapses. Thelow-level description of the model is below.

<rule> name=‘QIF2’ // only the v equation defined code =‘v+=(0.04*v+5).*v+140+I; I=4*rand( )/MAX_RAND’ <rule> name=‘spike’ code= ‘v>30’ <unit_type> name = ‘exc’ update_rule = ‘u+=0.02*(0.2*v−u);I−=u;’ update_rule = ‘QIF2’ event_condition = ‘spike’ after_event_rule =‘v=−65; u+=8; last_spike=now’ init = ‘analog v=−70, u=−14, I=0; intlast_spike=−1000’ <unit_type> name=‘inh’ // inhibitory neuronupdate_rule = ‘u+=0.1.*(0.2*v−u); I−=u;’ update_rule = ‘QIF2’event_condition = ‘spike’ after_event_rule = ‘v=−65; u+=2;’ init =‘analog v=−70, u=−14, I=0; int last_spike=−1000’ //Ne records of theclass <unit of exc> unit_id = 1:800 // i=1:Ne //Ni records of the class<unit of inh> unit_id = 1:200 // i=1:Ni <rule> name = ‘EPSP_plus_LTD’code = ‘I+=w; sd−=LTD(now-last_spike); last_active=now’ init = ‘LTD ={array};’ <rule> name = ‘LTP’ code = ‘sd+=LTP(now-last_active);’ init =‘LTP = {array};’ <rule> name = ‘Synaptic_Maintenance’execution_condition = ‘now%1000==0’ update_rule = ‘w += 0.01+sd; if(w<0) w=0; if (w>10) w=10; sd *= 0.9’ <synaptic_type> name = ‘GLU’presynaptic_event_rule = ‘EPSP_plus_LTD’ postsynaptic_event_rule = ‘LTP’update_rule = ‘Synaptic_Maintenance’ init = ‘analog w=6, sd=0; intlast_active=−1000;’ <synaptic_type> name=‘GABA’ presynaptic_event_rule =‘I−=5’ delay=1 // Default delay; the same for all synapses //Ne*Mrecords of the class (exc-> exc or inh) <synapse of GLU> pre = exc[i]//i=1:Ne post = exc[j] or inh[j] // random, between 1 and Ne or 1:Nidelay  // a random number between 1 and D //Ni*M records of the class(inh->exc) <synapse of GABA> pre = inh[i]// i=1:Ni post = exc[j]  // arandom number between 1 and NeEND 3.0

The END format 3.0 implements several major changes when compared to theEND 2.0 format. These include:

-   -   Introduction of one-way junctions    -   Splitting of the junction update_rule into two rules: the        update_rule (configured to modify junction variables); and the        delivery_rule (to configured modify the post-synaptic unit        variables)    -   Removal of the postsynaptic_event_rule    -   Splitting of the presynaptic_event_rule into: the prepost_rule        (for LTP part of STDP); the postpre_rule (for LTD part of STDP);        and the delivery_rule (for delivering PSP)    -   Atomic addition for the delivery_rule (for junctions and        synapses)    -   Removal of the clock-based synaptic update rule (it can be        implemented via postpre_rule)    -   Implementing global variables via links to instance variables.

All names and statements in END 3.0 have similar meaning to those in END2.0 unless stated otherwise. For END 3.0, the syntax exc:3 is used torefer to the instance 3 of the type ‘exc’.

Synaptic Rules

The presynaptic event rule can comprise multiple independent rules. Forthe purposes of this description, the designators t1 and t2 denote thetimes of spikes of the pre-synaptic neuron arriving at the post-synapticunit (i.e., conduction delay is already incorporated into t1 and t2 ),where the t2 corresponds to the current simulation time (also referredto as ‘now’).

The prepost rule may be executed at any time before t1 to implement theLTP part of STDP that would correspond to a pair of pulses withpre-synaptic neuron firing at t1 and a subsequent post-synaptic neuronfiring after t1 but before or at t2 . While the prepost_rule rule hasaccess to the system variables prepre (now−t1) and prepost(post_spike−t1), it does not have access to any post unit variables orthe system variable at time t2 (‘now’), as it is not clear when thisrule is called. If prepost_mode=11 (1-to-1), then each pre-synapticspike triggers only 1 call for prepost_rule. If prepost_mode=1A(1-to-all), then each pre-synaptic spike triggers prepost_rule for allsubsequent post-synaptic spikes (with its own prepost variable), up tothe moment of the next pre-synaptic spike. The parameter prepost_max (ifgiven) further limits the span of time after the pre-synaptic spikeduring which to consider post-synaptic spikes for prepost_rule. Forexample, if the LTP window of STDP is only 50, then there is no point ofconsidering pairs of pre-post spikes with the interval greater than 50.In another embodiment, prepost_rule may be called when the earliest postspike after t1 occurs later than t1+prepost_max. In certain embodiments,the rule is not called if the post spike never occurs during the periodbetween t1 and t2.

The postpre_rule is typically executed just before time t1 in order toupdate the synaptic variables based on the timing of the previouspre-synaptic spike (prepre=t2 −t1) and the last post_synaptic spike(postpre). The latter variable is typically provided even if a longperiod of time has elapsed since the previous post spike occurred. Thevariable ‘now’ points to the current time, and all variables from thepost-synaptic unit are available for reading.

The delivery_rule is typically called at time t1, but after thepostpre_rule updated the synaptic weights. The delivery_rule has accessto all the variables of the latter rule, plus has write access foratomic addition to the variables of the post unit.

Listing 3 <rule>   name   exec_condition   code   init <unit_type>  name   update_rule   event_condition   after_event_rule   init <unitof unit_type>   unit_id   init <junction_type>   name   update_rule  delivery_rule   init <junction of junction_type>   pre   post   init<synaptic_type>   type   prepost_rule

In the code example shown in Listing 3, the rule is triggered before t2and it modifies the synapse. The rule can read and write synapticvariables but does not have access to any variables from thepost-synaptic unit. The rule has access to prepre=t2 −t1 and prepost(post spike−t1).

-   -   prepost_mode

Two modes are supported, 11 (1-to-1) and 1A (1-to-all). The former callsthe rule at most once, while the latter calls multiple times for eachpost unit spike after the pre unit last spike. Default: 11

-   -   prepost_max        limits the scope of time after the pre unit spike to consider to        form pre-post pairs. All post spikes after t1+prepost max will        be ignored.    -   postpre_rule        the code or rule name that is triggered at t2 and modifies the        synapse. It can read and write synaptic variables and has read        access to variables from the post-synaptic unit. It has access        to prepre, postpre, and now=t2.    -   delivery_rule        the code or rule name that is triggered at t2 and modifies        variables of the post unit. It has read access to synaptic        variables, prepre, postpre, and now=t2 . This code is atomic        addition.

<synapse of synaptic_type>   pre   post   delay   initIdentifying Event-Triggered Pre-Unit Variables

In certain embodiments, it can be desirable to model short-term synapticplasticity, which is triggered by pre-synaptic spikes. Often, thisrequires having a variable or a vector of variables that is modified byeach pre-synaptic spike and then evolves according to some equation, butonly values of this variable at the moment of pre-pulses are needed. Inthis case, the variable may be part of each synapse. However, since thevalue of all such variables is the same for all synapses, a compiler(linker) from END to an engine can remove these variables from synapsesand use a single pre-synaptic variable instead, subject to a “pre-rule”.Alternatively, the END format may have a special tag or a label, or astatement that would help the compiler to identify such pre-eventtriggered variables in synaptic event rules or pre-synaptic unit eventrules.

If the END program is distributed among multiple engines, then eachengine can transfer the value of such variables with each pre-synapticspike. Alternatively, each engine that receives synapses from suchpre-synaptic unit can keep a local copy of the variable, updating it thesame way as it is updated in the engine that hosts the pre-synapticunit.

EXAMPLE 4 Spnet

The spnet network typically comprises N=Ne+Ni=1000 neurons, where Ne=800excitatory neurons and Ni=200 inhibitory neurons. Each neuron typicallycomprises M=100 synapses per neuron. All excitatory synapses are plastic(STDP), with a random delay ranging between 1 ms and D=20 ms. Theinhibitory->excitatory synapses are non-plastic with a delay of D=1 ms.There are no inh->inh synapses. The low-level END 3.0 description of themodel is expressed as follows.

Listing 4 <rule>   name=‘QIF2’ // only the v equation defined   code =‘v+=(0.04*v+5).*v+140+I; I=4*rand( )/MAX_RAND’ <rule>   name=‘spike’  code = ‘v>30’ <unit_type>   name = ‘exc’   update_rule =‘u+=0.02*(0.2*v−u); I−=u;’   update_rule = ‘QIF2’   event_condition =‘spike’   after_event_rule = ‘v=−65; u+=8;’   init = ‘analog v=−70,u=−14, I=0;’ <unit_type>   name=‘inh’ // inhibitory neuron   update_rule= ‘u+=0.1.*(0.2*v−u); I−=u;’   update_rule = ‘QIF2’   event_condition =‘spike’   after_event_rule = ‘v=−65; u+=2;’   init = ‘analog v=−70,u=−14, I=0;’   //Ne records of the class <unit of exc>unit_id = i //i=1:Ne   //Ni records of the class <unit of inh>   unit_id = i // i=1:Ni<rule>   name = ‘LTD’   code = ‘sd−=LTD(postpre); w += 0.00001*prepre +sd*10*(1− 0.9999{circumflex over ( )}prepre); if (w<0) w=0; if (w>10)w=10; sd *= 0.9999{circumflex over ( )}prepre)’   init = ‘LTD ={array};’   // sd‘=−sd/10 sec; 0.9999{circumflex over ( )}x =exp(−x/10000); the rule could be optimized so that 0.9999{circumflexover ( )}x is computed only once: w+10*sd; sd*=..; w−=10*sd;’ It couldbe further optimized so that 10* is removed (but LTP and LTD tables arescaled up by 10). <rule>   name = ‘LTP’   code = ‘sd+=LTP(prepost);’  init = ‘LTP = {array};’ <synaptic_type>   name = ‘GLU’   prepost_rule= ‘LTP’   postpre_rule = ‘LTD’   delivery_rule = ‘I+=w’   init = ‘analogw=6, sd=0;’ <synaptic_type>   name=‘GABA’   delivery_rule = ‘I−=5’  delay=1 // Default delay; the same for all synapses   //Ne*M recordsof the class (exc-> exc or inh) <synapse of GLU>   pre = exc:i// i=1:Ne  post = exc:j or inh:j // random, between 1 and Ne or 1:Ni   delay  //a random number between 1 and D   //Ni*M records of the class (inh->exc)<synapse of GABA>   pre = inh:i// i=1:Ni   post = exc:j  // a randomnumber between 1 and NeEvent-Driven Architecture

An Event Driven Architecture (EDA) may be defined as a generalization ofthe END format that acts as an abstraction layer configured to isolatecomputational description from the neuroscience description of themodel. The EDA defines memory management, parallelism, and rulestriggered by events and enables compilation of the END-code directlyinto EDA code.

The events in END format and EDA architecture correspond to pulses,whether physical or virtual, software representation of pulses,stereotypical bursts of pulses, or other discrete temporal events.

EDA Memory Management

EDA memory management differs (from the point of view of ownership ofvariables) from the END framework in the following:

Units own their own variables. When an update rule for a unit A isexecuted, it does not require access to variables of any other units ofthe network. Conversely, no rules being executed by other units requireaccess to the variables of the unit A.

Synapses own their own “synaptic” variables, such as weights, variablessuch as last_active, etc., and they may refer to (read from and writeto) certain variables in the post-synaptic unit. When eitherpresynaptic_rule or postsynaptic_rule is executed, two or more synapsesmay try to access and modify the same variable of the post-synapticunit. However, the synapses do not compete for their own synapticvariables.

Junctions own their “junction” variables, but they access and modifyvariables in the unit_1 and unit_2. When junctions are executed, thereis no competition for parallel access to their junction variables, butthere may be competition for the access to unit_1 and unit_2 variables.

Thus, units, synapses, and junctions may be treated as units, doublets,and triplets in terms of ownership of variables. Units own a set ofvariables, synapses own one set of variables and refer to another setowned by units. Junctions own one set of variables and refer to twoother sets of variables owned by two units. This nomenclature can beapplied to describe the END 1.0, 2.0 and 3.0 formats, as well asexemplary embodiments below.

Rules and Events

The class member Event_condition triggers execution of the followingrules:

-   -   After_event_rule that acts on the unit that has triggered the        event (the trigger unit);    -   presynaptic_event_rule that acts on synapses (doublets) that        point from the trigger unit to other units;    -   postsynaptic_event_rule that acts on synapses (doublets) that        point to the unit from other units

The class member Update_rule is executed at every time step of thenetwork simulation and it updates variables in units, synapses (possiblyvia a background process), and junctions, i.e., in units, doublets, andtriplets.

Units, doublets, and triplets as elements may be referred to as thenetwork elements. The END format, therefore, defines (i) elements, (ii)rules that act on elements, and (iii) events that are triggered byelements and cause execution of other rules that act on other (target)elements.

Definition of EDA Instruction Set

The objectives behind the development of the EDA framework according tocertain aspects of the present invention include:

-   -   elements (units, doublets, triplets, etc.) that have their own        variables and in addition may refer to variables in other        elements;    -   clock-driven rules (rules) that act on variables in elements;        and    -   event-driven rules (events) that are triggered by some elements        and act on variables in other (target) elements.

The EDA instruction set starts with defining rules that act on abstract(symbolic) variables. Rules may include other rules defined earlier, soas to form a directed graph of rules with no cycles. Elements aredefined by the clock-driven rules that act on the same or otherelements. Events are defined by trigger condition and target rule thatare applied to other elements.

One example of an EDA instruction set is shown below in Listing 5. Boldkeywords in Listing 5 denote components of the END instruction set,whereas non-bold words denote user-defined names and values.

Listing 5 rule_name = rule code = ‘ . . . ’ code = another_rule_nameinit = ‘ . . . ’

In Listing 5, the identifier “code” can refer to any string of code, orthe name of another rule defined previously. While C-code syntax is usedin the Listing 5, it will be appreciated by those skilled in the artsthat any other language description (including, for example, C#, Python,Perl, etc.) is equally applicable to the invention. There may bemultiple codes and rules included within a rule that can be executed inthe order of inclusion. In certain embodiments, rules that are used inmultiple element types can be defined separately, so that the engine canuse its acceleration tricks to execute such rules in parallel. Thestatement “init” defines static (global within the rule) variablesneeded to execute the rule, e.g., it defines lookup tables. The “code”may refer to the static variables defined in “init”, to instancevariables defined in the element (see below) or to other instancevariables defined in other element types, e.g., “I+=A.w+B.w” refers toan instance variable I, and to variables w defined in an elements A andB.

element_name = element rule = rule_name rank = a number or range ofnumbers init = ‘ . . . ’

The latter is a definition of an element type. Here, “rule” refers to arule defined earlier or to a string of code. The parameter “rank”specifies the rank order of execution of the rule within a clock cycle.It takes fixed-point value from the interval [0 1]. E.g., rank=0.45means that this rule will be executed after all rules with lower rankand before all rules with higher rank, but in parallel with the rulesthat have the rank 0.45. If rank is given as an interval, e.g.,rank=min:max, then the engine has the freedom of executing this rule anytime after all rules with rank<min and before all rules with rank>max.If “rank” is missing, it is equivalent to the default value rank=0:1,i.e., the engine has complete freedom of selecting when to execute thisrule. If the rank is greater than 1, then the engine skips cycles toexecute the rule. For example, rank=2.45 will cause the engine to skip 2cycles until next execution of the rule. The string “init” defines thenames of instance (local) variables of the element and sets theirdefault initial values.

id = element_name A = other_element_name.id B = other_element_name.idvariable_name = value

The latter is a definition of an instance of the element type. Here,“element_name” is the name of an element type defined earlier. The lines“variable_name=value” may set values of instance variables that aredifferent from the default values defined in the “init” statement in theelement definition. If the rule_name in the element definition refers toother elements (which is the case for doublets and triplets), then theids of these elements must be specified here. Notice that one can useany variable name, not necessarily A and B (or Unit_1 and Unit_2 inEND), to refer to other elements.

event_name = event trigger_condition = rule_name trigger_rank = numberor number range target_code = rule_name target_rank = number or numberrange

The latter is a definition of an event type. Here, “trigger condition”is a name of a rule or a string code that returns true/false value. Thiscondition (applied to elements; see below) is evaluated at the rankgiven by “trigger_rank”. When the condition is true, it triggersexecution of the “target_code” in the target element (defined below) atthe rank “target_rank”.

event_name trigger = element_name.id target = element_name.id

The latter is a definition of an instance of the event type. Itspecifies which element is the “trigger” and which element is the“target” of the event.

EXAMPLE 3 Spnet with No Delays

A network of randomly connected 800 excitatory and 200 inhibitoryneurons (100 of exc->all and inh->exc connections) can be defined withexcitatory synapses subject to STDP and no conduction delays (forconduction delays, see next example).

Listing 6   QIF = rule   code = ‘v+=0.5f*((0.04f*v+5.0f)*v+140.0f−u+I);v+=0.5f*((0.04f*v+5.0f)*v+140.0f−u+I); I=0.0f;’   exc = element   code =‘u+=0.02f*(0.2f*v−u);’   code = QIF   rank = 0   init = ‘float v=−65.0f;float u=−13.0f; float I=0.0f; int last_spike=−1000’   1:800 = exc   inh= element   code = ‘u+=0.01f*(0.2f*v−u);’   code = QIF   rank = 0   init= ‘float v =−65.0f; float u=−13.0f; float I=0.0f; int last_spike=−1000;’  1:200 = inh   spike = rule   code = ‘v>30’   after_spike_reset_exc =event   trigger_condition = spike   trigger_rank = 0.1   target_rule =‘u+=8; last_spike=now’   target_rank = 0.2   after_spike_reset_exc  trigger = exc.1:800   target = exc.1:800   after_spike_reset_inh =event   trigger_condition = spike   trigger_rank = 0.1   target_rule =‘u+=2; last_spike=now’   target_rank = 0.2   after_spike_reset_inh  trigger = inh.1:200   target = inh.1:200   inh_syn_event = event  trigger_condition = spike   trigger_rank = 0.1   target_rule =‘I−=5.0f’   target_rank = 0.3   // make 200*100 such entries  inh_syn_event   trigger = inh.<random number between 1 and 200>  target = exc.<random number between 1 and 800>   weight_update = rule  code = ‘w += 0.01f + sd; if (w<0.0f) w=0.0f; if (w>10.0f) w=10.0f; sd*=0.9f’   exc_synapse = element   code = weight_update   rank =999:1000// any time within that cycle   init = ‘float w=6.0f; float sd =0.0f; int last_active = −1000’   id = exc_synapse   post = <eitherexc.id or inh.id with id = random>   PSP_LTD_rule = rule   code =‘post.I += w; sd −= LTD(now - post.last_spike); last_active = now’  init = ‘float LTD = {. . . }’   PSP_LTD_event = event  trigger_condition = spike   trigger_rank = 0.1   target_rule =PSP_LTD_rule   target_rank = 0.3   PSP_LTD_event   trigger = exc.<eachid>   target = exc_synapse.<each corresponding id>   LTP_rule = rule  code = ‘sd += LTP(now-last_active)’   init = ‘float LTP = {. . . }’  LTP_event = event   trigger_condition = spike   trigger_rank = 0.1  target_rule = LTP_rule   target_rank = 0.4   LTP_event   trigger ={for each exc.id and inh.id}   target = exc_synapse.<each correspondingid>

The linker is typically configured to group all events triggered by‘spike’ rule (that are within with the same rank) into a single event,so that the computational engine executes the ‘spike’ condition onlyonce per model simulation step for each unit.

In certain embodiments, the rank information in provided in thedefinition of the rule; this way, there is no need to repeat ranks inthe definition of events.

Elementary Network Interface

Elementary network interface (ENI) can be implemented as a communicationprotocol that implements data exchange between two simulations describedin the low level description END format or any other entity that isrequired to send/receive data to/from a simulation (e.g. input device,visualization/debug tool etc.). The ENI is strongly entwined with ENDitself, and it can be used to partition large END files into smallerpieces, ensuring correct results. Therefore, certain parts of ENIrequire detailed knowledge of the END engine handling of communicationevents.

Referring now to FIG. 3, a generalized communication framework 300between two computational engines 302 (each running an END modelsimulation) is shown and described. The ENI communication protocol isimplemented in some physical means of communication (e.g. USB/Bluetoothfor peripherals or Ethernet/Infiniband, for more demanding situations).Each computational engine 302 is required to implement the ENI (thecommunications pipe denoted as 306 in FIG. 3) on top of the transportlayers available (the communications pipe denoted as 308 in FIG. 3).Note that ENI forms a layer of communication between models described byEND, and not between the engines 302 themselves.

In certain embodiments, the engines 302 are connected by the low leveltransport layer may discover each other and pair automatically. Manualsetup is also possible (e.g. for engines connected via IP protocol). Thecommunication specification file (ENI file) is supplied along with theEND file to the engine. Once the engine discovers that it is paired withanother engine that runs the right END file, the ENI channel isnegotiated and established (green pipe in FIG. 1). The ENI communicationspecification file can be regarded as a mapping, which helps bothparties to understand each other and target the right units of the rightclasses.

2. ENI Channels

FIG. 4 shows a block diagram of ENI communications channel 306 of FIG.3. The channel 306 is defined by its endpoints (the IDs of the low levelEND description, such as the END A and END B in FIG. 3) and a set ofparameters that describes how the communication is performed and whattype of information is communicated. The communication channel 306 isunidirectional, going from left to right direction, and is defined bythe sending entity 402 and the receiving entity 404. The data transferis one way (though negotiation and meta information in the transportlayer are not restricted).

Typically, the ENI channel parameters include:

-   -   Sender and receiver END ID's and an identifier that uniquely        identifies the channel    -   Sender and receiver classes    -   Sender and receiver class instances (enumerated by their number        within the class)    -   Content: events/spike notifications or values of certain        parameters    -   Format of the data sent    -   Modes of operation (sync, async) and their parameters        (frequency, phase shift etc.)        2.1 Content and Format

In one implementation, the ENI communication channel is be used toexchange (i) spike (event) notifications and (ii) values of selectedclass parameters (variables). These two content types require differentdata sent through the channel, namely:

-   -   Unit indices (for spike notifications)    -   The actual values of variables (of all instances transmitted by        the channel)

In one implementation, network unit indices interleaved with valuesvariables. Such implementation is applicable when the values need to besent only for the units that experienced an event (spike), so as tominimize network traffic. To summarize, the following data formats aresupported:

-   -   Indices (some units) either with values or not. If the values        are missing, then the data is interpreted as a spike        notification.    -   No indices (all units) but only values. (If the values are        missing then the data is interpreted as a spike notification of        all the units involved; this is an unlikely case, left for        consistency).

Typically, these two content types (i.e., events and data) are not mixedin a single ENI channel instance. In certain embodiments, whenever theENI channel is set to transmit events/spike notifications, the targetunits are (“artificially”) fired; that is, the event is scheduled on thereceivers spike queue but any post event actions like LTP or reset arenot performed. In one example, the units that can be fired externally donot have any local incoming synapses that are subject to plasticityrules (e.g., LTP). In another example, the units are configured torespond to both the external firing triggers and plasticity rules suchthat whenever they are fired externally, the post event rues are notinvoked. Such configuration ensures simulation consistency and enablessplit-simulations produce the same outcome as a “single simulation”.Therefore, when partitioned appropriately, it is always (considering therestrictions above) possible to obtain the same results with the splitssimulations as with the single simulation. In one example, the modelpartitioning is facilitated via an introduction of specialfake/receiving units as required.

FIG. 4 illustrates content, formats and expected behavior in the ENIcommunications channel. In the case of transmitting values of variables,the channel description specifies the set of variables of the sender andreceiver classes. In other words, ENI specifies which variables withinthe source class will be mapped to which variables in the target class.The consistency requirement is that either the internal representationof the variables sent through the channel are compatible between senderand receiver or the communication channel performs all necessaryconversions. After each communication event, the values in the targetclass are updated to the new values.

In certain embodiments, the ENI channel transmits data related to unitsin END format. In certain embodiments, the data related to synapses orjunctions (e.g., synaptic weights or other variables) are transmitted.

2.2 Mapping of Units

The ENI channel can introduce a mapping from certain elements of thesource unit class in the END format to certain elements of the targetclass. Each channel establishes communication between one sender classand one receiver class. The mapping establishes the indices that will besent through the wire (refer to the FIG. 4), if spike notifications arebeing sent, or the order of values if parameter values are communicated.

2.3 Sending/Receiving Frequency

The ENI channel need not send information at every model simulationcycle. The ENI files specify the periods T1, T2 (expressed in enginemodel simulations cycles) of sending/receiving. The designator T1corresponds to the sending side period (so the data will be sent onlyevery T1 cycles), T2 describes the receiver side (data is expected tohave been delivered to the simulation every T2 cycles). The data may bedelivered to the engine at any point, but the engine will keep (buffer)it and will make it available to the running simulation at theappropriate receiving point.

3. Modes of Operation

The ENI communication channel is typically configurable to operate intwo modes—synchronous and asynchronous. In synchronous mode, thetransmission and delivery is synchronized to the nearest simulationcycle. In asynchronous mode, the (input) data are continuously providedto the computational engine and delivered to the respective units of thesimulation instance whenever it is ready. While the synchronous modeensures timely delivery of data it may cause serious performancebottlenecks for high input data rates. Conversely, the non-synchronousmode may cause undefined model behavior due to variable data deliverytimes.

FIG. 5 presents examples of modes of operation of the ENI (scheme).Combined two formats, two content types and two modes of operation forma cube as illustrated in the embodiment FIG. 6. In certain embodiments,the ENI is extended in terms of possible data formats and in the futuremay include content aware compression etc.

3.1 Synchronous Mode

In one implementation of the synchronous mode, it is assumed that thereceiving engine cannot proceed through the data receiving point unlessthe necessary data has arrived (so the receiver synchronizes with thesender). The channel in that mode specifies additional property—namelythe phase shift S. If the shift S>0 the engine will proceed with thesimulation if the data packet sent S cycles ago has arrived (sinceengines are synchronized it does not matter whether these are sender orreceiver cycles). The phase shift allows for better utilization of thecommunication channel whenever the actual structure of neuro-simulationallows for it (that is certain projections sent through ENI channel havedelays that can be used to relax requirements for the channel andintroduce the shift, see FIGS. 7 and 7A). The underlying transport mayintroduce priorities to channels based on their phase shift (the timerequired to deliver the data).

The sender can proceed with other tasks after the data is sent withoutwaiting for any delivery notification, however if the message is notdelivered, the next attempt to send data over the channel will hold thesimulation. (The sending engine will not proceed if more than Snon-confirmed deliveries occur in a synchronous channel with phase shiftS).

3.2 Asynchronous Mode

In certain embodiments, particularly where applicable to thenon-synchronous (i.e., asynchronous) mode, the frequency of sending andreceiving data is specified, but the engine does not stop its executionuntil the data are sent. On the receiving side, the asynchronous modedoes not impose any data delivery timing restrictions. In one example,the computational engine is configured to receive the data arriving inindivisible chunks (block transfer). In another example, the data aretransferred via a stream (streaming transfer). Other examples arepossible, such as, for example, a combination of block and streamedtransfer. In the block transfer sub-mode, the transmitted message isassumed to be delivered only after all the data within the block hasbeen delivered to the receiver (e.g., the receiver 404 in FIG. 4) andthe communication transaction is completed. In the streaming sub-mode,the data that becomes available at the receiver is gradually transmittedto the engine, regardless of whether the transmission transaction hascompleted or not.

In the asynchronous block mode it may be assumed that only the latestmessage is actually delivered to the engine, while others receivedbefore the engine encountered the receiving point are discarded (Itmight be useful when a real-time input device (like a camera) is sendingdata in non synchronous mode faster than the engine can handle). Theasynchronous streaming mode accumulates all the data, and delivers it atthe closest receiving point.

FIG. 7A illustrates one example of fully synchronous communicationbetween two computation engines 702, 704. The embodiment of FIG. 7 canensure timely data exchange between the engines 702, 704, and can reducecommunications delays, thereby minimizing potential communicationchannel jamming due to delays that may be associated with heavy anduneven data flows in large, real-time neuronal model simulation runs. Inone example, various data transfer optimization are used, whichsignificantly expand the communication bandwidth. In FIG. 7, the eventindices and data values are sent through separate ENI channels (denotedby the heavy and thin arrows 706, 708, respectively, in FIG. 7), andhave separate receiving points

FIG. 7B illustrates one example of synchronous communication with aphase shift of one system clock cycle (simulation step) (S=1 in bothdirections). The communication channel is used more evenly due to thewindow overlap (as indicated by the vertical arrows 752, 754 in FIG. 7B,but spikes and values arrive with a delay of 1 ms/step.

4. Sending and Receiving Points

The sending point refers to a logical constrict of the simulation modelwhich is used to describe the data and events that become availableimmediately after processing of units during model execution by thecomputational engine. Similarly, the receiving point is used to describedata staging container used before processing junctions during eachsimulation cycle. Such an arrangement leaves a short communicationwindow but the following optional optimization may be possible:

The sending driver processes units in a priority order and sends out thedata as soon as they become available while other units are still beingprocessed by the engine in parallel.

The receiving driver executes local junctions while still awaiting forthe necessary data to arrive.

If the channel sends spike notifications, the computational engine canprocess synapses from local units before receiving the data on spikesfrom non-local units.

In such a case the communication window can be significantly expanded(as denoted by dotted arrows in FIG. 7B).

5. An Example of Communications Definitions Using ENI

Listing 7 illustrates one example of an ENI definition file (known tosender/receiver drivers) useful in a network simulation that uses END.It will be appreciated by those skilled in the arts that while theexamples below shows the data required to set up a channel, the actualformat of that file might change to XML or some other format.

EXAMPLE 4

Example 4 describes engine simulations where ‘Retina’ END file sendsindices of selected units from class ‘RGC’ that fired to the enginerunning ‘LGN’ END file. Selected elements of class ‘exc’ are fired. Thecommunication is typically synchronous, synchronization points appearevery cycle on both sender and receiver, and the channel has no shift(delay).

Listing 7   ENI_ID = ‘CommC’   SOURCE_ID = ‘Retina’   // id of thesource END file (simulation)   TARGET_ID = ‘LGN’   // id of the targetEND file (simulation)   MODE = SYNC   T1=1   // sender sync frequency -when to send data (in simulation cycles)   T2=1   // receiver syncfrequency - when to expect data (in simulation cycles)   S=0   //receiver phase shift   FORMAT = INDICES   // Only spiking units will beobserved by the channel   SENDER_VALUES = NONE   // only indices will besent, that is channel will fire target units   RECEIVER_VALUES = NONE  SENDER_CLASS = ‘RGC’   RECEIVER_CLASS = ‘exc’   NUMBER_OF_UNITS = 500  // How many units will be observed by the channel?   SENDER_UNITS = 8423 395 39 201 34 . . .   RECEIVER_UNITS = 33 45 67 98 18 34 19 . . .

EXAMPLE 5

Example 5 illustrates engine simulations where the ‘Camera’ END willasynchronously send values of ‘R, G, B’ variables in class Pixel, tovariables ‘Red,Green,Blue’ of class RGC in the Retina END file.

Listing 8   ENI_ID = ‘ENI2’   SOURCE_ID = ‘Camera’   // id of the sourceEND file (simulation)   TARGET_ID = ‘Retina’   // id of the target ENDfile (simulation)   MODE = ASYNC   STREAM = NO   // the receiver willnot accumulate data (only the latest data will be delivered to theengine)   T1=1   // sender sync frequency - when to send data (insimulation cycles)   T2=2   // receiver sync frequency - when to expectdata (in simulation cycles)   FORMAT = NOINDICES   // All values will besent every time   SENDER_VALUES = ‘R,G,B’   // values of those variableswill be sent   RECEIVER_VALUES = ‘Red,Green,Blue’   // Values of thosevariables will be updated   SENDER_CLASS = ‘Pixel’   RECEIVER_CLASS =‘RGC’   NUMBER_OF_UNITS = 1024   // How many units will be observed bythe channel?   SENDER_UNITS = 1 2 3 4 5 6 7 8 9 10 11 . . .  RECEIVER_UNITS = 33 45 67 98 18 34 19 . . .

The table shown in FIG. 13 lists possible values of communicationsparameters used in Listing 8:

Large Model Partitioning Using ENI

In certain embodiment, many ways exist to handle a largeneuro-simulation model (defined, for example, using a high leveldescription format). In one approach, the processing is performed by asingle processing computational engine. In another approach, theprocessing is distributed within a set of several computational engines(computing nodes). In order to achieve efficient workload distributionthe model needs to be partitioned. In one example, one large low-leveldescription (END file) of the model is generated and the partitioning isperformed by the distributed computational engine. This example offersbenefits of real time load adjustment and rebalancing, but istechnically more complex and requires an advanced distributed loadcontroller. In another example, the model is partitioned into a set ofEND files and ENI communication channels, which are executed separatelyfrom one another. There is always a way to split a neuro-simulation intoparts using ENI, possibly by introducing additional “fake” units.

FIGS. 8 and 9 illustrate one example of model partitioning according tocertain aspects of the present invention. FIG. 8 shows the END model 800comprising of several units 802, synapses 804 and junctions 806 anddescribed using the END file END0. The numerals along the synapses 804denote synaptic delays. The model 800 simulation is executed using asingle computational Engine0.

FIG. 9 illustrates partitioning of the model 800 into two partitions 910and 920, described using the END files END1, END2, respectively. Thepartitions 910, are interconnected using three ENI interfaces: ENI1,ENI2, ENI3, denoted as 912, 914, 916, respectively in FIG. 9. Someadditional ‘fake’ units have been introduced (rectangles marked as 902).Because the ENI 1 channel has a phase shift S=2, the channelcommunication delay is compensated by using smaller delays of the targetsynapses, as illustrated by a comparison of the synapses 804 and 904 inFIGS. 8 and 9, respectively. Note, that such implementation is possiblewhen there are no synapses of minimal delay (e.g., 0) in the originalmodel (the model 800) along the partition line that are replaced by anENI channel. The compiler from a high-level definition language can takeinto account the delays while splitting the simulation to optimizecommunication (e.g. enlarge the communication window, balance the amountof data sent etc.). Simulation of the model 900 is executed using twocomputational engines: Engine 1 and Engine 2, as illustrated in FIG. 9.The multi-partition simulation 900 is capable of producing the samesimulation results, compared to the single partition simulationimplementation 800, providing the distributed computationalEngine1/Engine2 has sufficient numerical precision to avoid roundingerrors.

In other embodiments of partitioned model (not shown), the followingfeatures may be implemented:

-   -   On the fly ENI channel setup and link negotiation (for dynamic        debugging and monitoring);    -   Support for additional data formats, e.g., analog.    -   Support for dedicated hardware infrastructure to run ENI;    -   A convenient and intuitive way to specify ENI format        Parallelization Via Splitting END

As described above with respect to the distributed model simulation(such as the partitioned mode 900 of FIG. 9), the model can be splitinto several partitions (e.g., the partitions 910, 920). Each partitionis executed on a single computational engine (engine1, Engine 2 of FIG.9. In one example, the computational engine comprises a singleprocessing unit (CPU) implementation. In another example, eachcomputational engine comprises multiple processing units (PU), such as,for example, CPU, FPGA, MCU, all running in parallel. Suchparallelization enables a substantial increase in the model simulationthroughput (that typically scales with the number of parallel PUs). Toenable parallel model execution, the simulation domain is divided intoseveral processing blocks (processing domains), each block beingassigned to one PU. Each processing block is configured to (i) keeptrack of local compartments, local spike queues etc.; (ii) store list(table) of incoming “synapses” (not applicable for END 3.0); and store slist of local junctions which can be processed without lockingCompartments are tagged with domain id-s, which must be informedwhenever they spike. When such an externally visible compartment spikes,the appropriate information is sent to neighboring domain, which doesthe rest of processing (synaptic queues etc).

For each step, the voltages of compartments connected via external(remote) junctions are sent to their target domains. Respectively,received voltages are used to compute junction currents.

The only data that the processing domains are exchanging are: (i) thespikes; and (ii) junction voltages (or some other variables that aretransmitted across junctions). Since most junctions will be of dendritictype (local), the amount of data in each exchange is typically not large(if the domain division takes dendritic junctions into account).

In another embodiment, a heterogeneous parallelized computational engineis implemented using multi-core symmetric multiprocessors (SMP)hardware. In one example, the SMP implementation also contains agraphical processing unit to implement.

END Engine Embodiments

FIGS. 10 through 12 describe different exemplary embodiments of theinvention that do not depend on the syntax of the END language. FIG. 10illustrates the three basic structures of the END engine, which can beimplemented on a standard CPU, GPU, or in an integrated circuit (e.g.,an ASIC). These are the “unit” 1001, the “doublet” 1011, and the“triplet” 1021. The END engine handles the execution of the unit,doublet, and triplet rules and the access to the memories of theseelements. The END formats above can be treated as the hardwarespecification language that would configure a semiconductor circuithaving such units, doublets, and triplets that executes a specifiedneuronal network.

In one example, each basic structure (unit, doublet, and triplet) isimplemented as a single thread on a multi-thread processor. In anotherexample, each structure is implemented as a super-unit, super-doublet,and super-triplet that comprises dedicated circuits configured toprocesses units, doublets, and triplets respectively using timemultiplexing (possibly, three different circuits for units, doublets,and triplets).

In one example, the unit 1001 represents a neuron or a part of a neuron,e.g., a dendritic compartment. In another example, the unit 1001represents a population of neurons, with the activity of the neuronrepresenting a “mean-firing rate” activity of the population or someother mean-field approximation of the activity of the population. Eachunit may have its own memory variables and an update rule that describeswhat operations must be performed on its memory. The operations can beclock-based, i.e., executed every time step of the simulation, or theycan be event-based, i.e., executed when certain events are triggered.The unit update rules typically do not involve variables that belong toother units. Hence the execution of the unit update rule is independenton the order of execution of unit update rules of other units, therebyenabling parallel execution of the unit update rules.

Depending on the values of the unit variables, the units may generateevents—pulses or spikes—that trigger synaptic events in other units viadoublets. For example, a unit 1002 in FIG. 10 can influence unit 1003via the doublet 1011, which represents a synapse from pre-synapticneuron (pre-synaptic unit 1002) to post-synaptic neuron (post-synapticunit 1003).

Units can also have after event update rules that are triggered afterthe event is triggered. These rules are responsible for modification ofunit variables that are due to the events, e.g., the after-spikeresetting of voltage variables.

Each doublet typically has its own memory variables, and it can accessvariables of the post-synaptic unit. The access includes read and write.Each doublet has a doublet event rule that makes a change to the doubletmemory, to implement synaptic plasticity, and the post-synaptic unitmemory, to implement delivery of pulses. The doublet event ruleencompasses all the synaptic rules described in the END formats above.

Since multiple doublets (e.g., 1016-1018 in FIG. 10) can connectcorresponding multiple pre-synaptic units 1006-1008 to a singlepost-synaptic unit 1009, it is desirable that the doublets modify thepost-synaptic unit memory in parallel or in arbitrary order and theresult be order-independent. This is easy to achieve if the operation onthe post-synaptic unit memory is atomic addition (as in GPUs), atomicmultiplication (which is equivalent to addition via logarithmictransformation), or resetting to a value (with all the doublets tryingto reset to the same value). It is also desirable that the post-synapticunit variable that is being modified by the doublet event rule is notused in the rule. Otherwise, the result may depend on the order ofexecution of doublet event rules.

In the context of neural computations, it is often desirable to have anaxonal conduction delay, so that there is a time-delay between an eventgenerated by a pre-synaptic unit and the execution of the doublet eventrule triggered by the unit. The delay can be implemented as a buffer, sothat each doublet receives the event with some delay. That is, the ENDengine registers an event generated by a pre-synaptic unit and puts aspecial marker into a delay-line queue depending on the magnitude of thedelay. The delay is counted down and then the event transmitted to thedoublet for the execution of the doublet event rule.

In certain embodiments, the doublets do not have access to pre-synapticunit variables. However, in some embodiments, doublets may have accessto some pre-synaptic unit variables. In one example, pre-synaptic unitmay have variables that are modified only during events triggered by theunit (i.e., event-based memory), and the modification does not depend onthe values of the other pre-synaptic unit variables. In such an example,such event-based memory may reside in the pre-synaptic unit memory, orequivalently, it may be treated as if a copy of the event-triggeredvariables resided at each doublet or shared among doublets

The doublet event rule is part of a class of doublet rules, which insome embodiments may also include post event rules and doublet updaterules, as illustrated in FIG. 11. The post event rule is a rule that istriggered by a post-synaptic unit and executed for all doubletsconnecting to the post-synaptic unit. In certain embodiments, the postevent rule of a doublet typically depends on the timing of theimmediately preceding pre-synaptic event. The doublet update rule is aclock-based rule that is executed for each doublet every time step,i.e., every system clock cycle.

In the embodiment illustrated in FIG. 12, the doublet event rule furthercomprises a timing event rule that (i) is configured based on the timingof events of the pre-synaptic and post-synaptic units; and (ii) controlsthe modification of doublet memory variables. The update rule,illustrated in FIG. 12, is at implementing Spike-Timing DependentPlasticity (STDP)—standard form of plasticity in spiking networks.

The timing event rule can further comprise a pre-post event rule thatimplements the part of the STDP that corresponds to pre-synaptic neuronfiring first (or the spike arriving from the pre-synaptic neuron first)and then the post-synaptic neuron firing thereafter, e.g., the pulses1202 generated before the pulses 1213, 1214. In the classical STDP thiswould correspond to the long-term potentiation (LTP) part of the STDPcurve. This rule modifies the memory of the doublet based on the timingsof the pre-synaptic and at least one subsequent post-synaptic firing,e.g., the pair 1202, 1213 (denoted by the line 1223); it typicallydepends only on the time difference.

The timing event rule can further comprise a post-pre event rule thatimplements the long-term depression part of the classical STDP whichoccurs when the post-synaptic unit fires first and then the pre-synapticunit fires after that, e.g., like the pulses 1211, 1212 generated beforethe pulse 1202. This rule modifies the doublet memory based on therelative timing of the pre-synaptic and post-synaptic firing; ittypically depends only on the time difference, i.e., on the differencebetween the timing of the pulses 1212, 1202.

Both, pre-post and post-pre event rules may depend on the values ofvariables in the post-synaptic unit memory.

In certain embodiments, it may be desirable to allocate memory ofdoublets according to their pre-synaptic units, so that all doubletshaving a common pre-synaptic unit are grouped together and allocatedconsequently in the system memory. This approach can minimize the randomaccess to system memory.

The doublet event rule can also comprise a pulse delivery rule thatmodifies the values of variables of the post-synaptic unit based on thevalues of doublet memory and the post-synaptic unit memory.

The description of doublets can be provided by the description ofsynaptic variables and rules in the END format.

As depicted in FIG. 10, supra, the triplet 1021 connects two units 1004and 1005. Such a triplet represents a junction in the END format. In oneexample, the triplet 1021 comprises a gap junction connection betweentwo neurons. In another example, the triplet 1021 corresponds to aresistance connection that connect two adjacent dendritic compartmentsof a neuron. In another example, the triplet 1021 is a combination ofboth junction types. The triplet comprises its own memory and it hasaccess to memories of both units. The triplet further comprises atriplet update rule that is executed every simulation time step. Thetriplet update rule may update the memory of each triplet and the memoryof at least one unit. In certain embodiments, the triplet update rulecan update memory of both units. Since it is desirable for such anupdate to be order-independent, the memory update of the at least oneunit is typically performed via atomic addition to a unit variable thatdoes not participate in the triplet update rule.

The description of the triplets can be provided by the description ofjunctions in the END format.

Certain embodiments can implement purely mean-firing rate models wherethere are no events, but where each unit transmits a signal to otherunits via triplet update rule.

Triplets can be allocated in the system memory according to thepre-synaptic unit so that all triplets originating from a commonpre-synaptic unit are grouped together. Triplets can also be allocatedaccording to the post-synaptic unit. In certain embodiments, tripletscan be allocated in the system memory according to the structure of theneural network. For example, if the neural network hasmulti-compartmental dendrites, then all triplets responsible forconnecting the dendritic compartments, can be allocated optimally as toimmunize memory access when the dynamical on the dendritic tree isevaluated during the system clock cycle.

Certain embodiments can implement purely event-driven architectureswhere units trigger events that deliver pulses to post-synaptic unitsvia doublets. Those units that received at least a single pulse duringthe clock cycle are tested for an event condition, and if it issatisfied, the after-event rule is executed and corresponding doubletevent rules are executed, so that pulses are delivered to other units.

Additional Descriptions of Certain Aspects of the Invention

The foregoing descriptions of the invention are intended to beillustrative and not limiting. For example, those skilled in the artwill appreciate that the invention can be practiced with variouscombinations of the functionalities and capabilities described above,and can include fewer or additional components than described above.Certain additional aspects and features of the invention are further setforth below, and can be obtained using the functionalities andcomponents described in more detail above, as will be appreciated bythose skilled in the art after being taught by the present disclosure.

Certain embodiments of the invention provide neuronal networks. Certainembodiments comprise a plurality of units, each having a memory updatedaccording to a unit update rule. Certain embodiments comprise aplurality of doublets, each doublet being connected to a pair of theplurality of units and configured to update the memory of a postsynapticone of the pair of units in response to an event received from thepresynaptic other of the pair of units according to a doublet eventrule. In certain embodiments, execution of unit update rules for theplurality of units is order-independent and execution of doublet eventrules for the plurality of doublets is order-independent. In certainembodiments, the doublet event rules are executable in parallel, andwherein the unit update rules are executable in parallel. In certainembodiments, for the each doublet, the execution of the correspondingdoublet event rule is triggered in response to a change in the memory ofthe presynaptic unit. In certain embodiments, for at least one doublet,there is a delay between occurrence of changes in the memory of itscorresponding presynaptic unit and updates to the memory of itscorresponding postsynaptic unit. In certain embodiments, the doubletevent rule for each doublet is triggered when its correspondingpresynaptic unit transmits an event to the each doublet.

In certain embodiments, each doublet has a memory that is updated inresponse to events received from its corresponding presynaptic unit. Incertain embodiments, the memory of the postsynaptic unit correspondingto the each doublet is updated based on the content of the memory of theeach doublet. In certain embodiments, updates to unit memories anddoublet memories are performed within a period of a time determined by asystem clock. In certain embodiments, all of the updates are completedbefore the period of time expires. In certain embodiments, the doubletevent rule for each doublet includes a timing event rule that controlsmodification of the memory of the each doublet. In certain embodiments,the timing event rule comprises pre-post event rule that controlsmodification of memory of the each doublet and that depends on thedifference between the timing of events transmitted by the presynapticunit and the timing of at least one subsequent event transmitted by thepostsynaptic unit. In certain embodiments, the timing event rulecomprises post-pre event rule that controls modification of memory ofthe each doublet and that depends on the difference between the timingof events transmitted by the presynaptic unit and the timing of at leastone preceding pulse transmitted by the postsynaptic unit.

In certain embodiments, the memory of each unit is updated by atomicaddition. Certain embodiments comprise a plurality of triplets eachhaving a memory, each triplet being configured to access the memory oftwo of the plurality of units. In certain embodiments, each triplet isoperable to update its own triplet memory and the memory at least one ofthe two units in accordance with a triplet rule. In certain embodiments,execution of triplet update rules for the plurality of triplets isorder-independent. In certain embodiments, the neuronal network isrepresented as a directed graph. In certain embodiments, therepresentation of a neuronal network is mapped to the interconnectedplurality of units independently of the physical and electricalstructure of the units, the doublets and the triplets. In certainembodiments, the neuronal network is expressed in a specificationprovided in non-transitory storage and coded according to a hardwaredescription language. In certain embodiments, the specification isoperable to reconfigure a semiconductor integrated circuit. In certainembodiments, each doublet is configured to update its memory accordingto a predefined post event rule that is triggered by its correspondingpostsynaptic unit. In certain embodiments, the post event rule dependson the difference between the timing of pulse of the postsynaptic unitand the timing of at least one preceding pulse of the presynaptic unit.

Certain embodiments of the invention provide methods of implementingneuronal networks. Certain embodiments comprise interconnecting aplurality of units using doublets configured to modify a memory of apostsynaptic unit responsive to an event received from a presynapticunit. Certain embodiments comprise configuring doublet event rules thatdetermine how the doublets respond to events. Certain embodimentscomprise configuring a unit update rule for each unit that controls theresponse of the each unit to memory updates initiated by a doublet. Incertain embodiments, execution of the doublet event rules isorder-independent and execution of the unit update rules isorder-independent.

In certain embodiments, configuring doublet event rules includesconfiguring each of the doublet event rules to be executed within a timestep having a duration determined by a system clock after receiving anevent during the time step. In certain embodiments, each presynapticunit maintains an event condition that controls transmission of eventsto a doublet. Certain embodiments comprise configuring an after-eventunit update rule for each presynaptic unit to be executed in associationwith the transmission of the events. In certain embodiments, theafter-event unit update rule causes modification of memory of the eachpresynaptic unit. In certain embodiments, each doublet modifies thememory of the postsynaptic unit memory by atomic addition. In certainembodiments, the doublet event rule for each doublet includes a timingevent rule that controls modification of a memory of the each doubletbased on timing of pulses associated with one or more of the pluralityof units.

In certain embodiments, the timing event rule comprises pre-post eventrule that controls modification of memory of the each doublet and thatdepends on the difference between the timing of pulses of a presynapticunit and the timing of pulses of at least one subsequent pulse of thepostsynaptic unit. In certain embodiments, the timing event rulecomprises post-pre event rule that controls modification of memory ofthe each doublet and that depends on the difference between the timingof pulses of the presynaptic unit and the timing of pulses of at leastone preceding pulse of the postsynaptic unit. In certain embodiments,execution of the doublet event rule for each doublet is triggered by anevent received from a presynaptic unit.

Certain embodiments comprise interconnecting a second plurality of unitsusing triplets configured to access memory of a pair oftriplet-connected units. Certain embodiments comprise configuring atriplet update rule for each triplets that controls updates to thememory of the each triplets and the memory of at least one of itscorresponding pair of triplet-connected units. In certain embodiments,execution of triplet update rules is order-independent. In certainembodiments, the update rule for each triplet responds to informationmaintained in memories of the pair of units connected by the eachtriplet. In certain embodiments, triplets update memories of units byatomic addition. In certain embodiments, each step of interconnectingpluralities of units, and each step of configuring rules are performedin accordance with a representation of a desired neuronal network. Incertain embodiments, the desired neuronal network is represented as adirected graph. In certain embodiments, the representation of a neuronalnetwork is mapped to the interconnected plurality of units independentlyof the physical and electrical structure of the plurality of units. Incertain embodiments, the representation of a neuronal network is mappedto the interconnected plurality of units independently of the physicaland electrical structure of doublets used to connect the plurality ofunits. In certain embodiments, the representation of a neuronal networkis mapped to the interconnected plurality of units independently of thephysical and electrical structure of the triplets used to the pluralityof units.

In certain embodiments, the pluralities of units, the doublets and thetriplets are embodied in a semiconductor integrated circuit. Certainembodiments comprise expressing the neuronal network in a specificationusing a hardware description language. In certain embodiments, thespecification is operable to reconfigure a semiconductor integratedcircuit. In certain embodiments, the specification is used tomanufacture a semiconductor integrated circuit. In certain embodiments,the first number of units includes certain of the second number ofunits. In certain embodiments, the doublet event rules are executable inparallel, the triplet update rules are executable in parallel, and theunit update rules are executable in parallel. In certain embodiments,the triplet update rules and the unit update rules are executed oncewithin a time step having a duration determined by a system clock. Incertain embodiments, the doublet event rule comprises pulse deliveryrule that modifies postsynaptic unit memory based on the content of itsassociated doublet memory. In certain embodiments, each doublet isconfigured to respond to events communicated by its correspondingpostsynaptic unit by initiating updates of doublet memory according to apredefined post event rule configured for the each doublet. In certainembodiments, the post event rule depends on the difference between thetiming of pulse of the postsynaptic unit and the timing of at least onepreceding pulse of the presynaptic unit.

While certain aspects of the invention are described in terms of aspecific sequence of steps of a method, these descriptions are onlyillustrative of the broader methods of the invention, and may bemodified as required by the particular application. Certain steps may berendered unnecessary or optional under certain circumstances.Additionally, certain steps or functionality may be added to thedisclosed embodiments, or the order of performance of two or more stepspermuted. All such variations are considered to be encompassed withinthe invention disclosed and claimed herein.

While the above detailed description has shown, described, and pointedout novel features of the invention as applied to various embodiments,it will be understood that various omissions, substitutions, and changesin the form and details of the device or process illustrated may be madeby those skilled in the art without departing from the invention. Theforegoing description is of the best mode presently contemplated ofcarrying out the invention. This description is in no way meant to belimiting, but rather should be taken as illustrative of the generalprinciples of the invention. The scope of the invention should bedetermined with reference to the claims.

What is claimed is:
 1. A system configured to provide a neuronalnetwork, the system comprising: one or more integrated circuits having aneuronal network embodied therein, the neuronal network comprising: aplurality of units, each having a memory updated according to a unitupdate rule; and a plurality of doublets, each doublet being connectedto a pair of the plurality of units and configured to update the memoryof a postsynaptic one of the pair of units in response to an eventreceived from the presynaptic other of the pair of units according to adoublet event rule; wherein execution of unit update rules for theplurality of units is order-independent and execution of doublet eventrules for the plurality of doublets is order-independent; wherein thedoublet event rules are executable in parallel; and wherein the unitupdate rules are executable in parallel.
 2. The system of claim 1,wherein for the each doublet, the execution of the corresponding doubletevent rule is triggered in response to a change in the memory of thepresynaptic unit.
 3. The system of claim 2 wherein, for at least onedoublet, there is a delay between occurrence of changes in the memory ofits corresponding presynaptic unit and updates to the memory of itscorresponding postsynaptic unit.
 4. The system of claim 2, wherein thedoublet event rule for each doublet is triggered when its correspondingpresynaptic unit transmits an event to the each doublet.
 5. The systemof claim 1, wherein each doublet has a memory that is updated inresponse to events received from its corresponding presynaptic unit, andwherein the memory of the postsynaptic unit corresponding to the eachdoublet is updated based on the content of the memory of the eachdoublet.
 6. The system of claim 5, wherein updates to unit memories anddoublet memories are performed within a period of a time determined by asystem clock, and wherein all of the updates are completed before theperiod of time expires.
 7. The system of claim 5, wherein the doubletevent rule for each doublet includes a timing event rule that controlsmodification of the memory of the each doublet.
 8. The system of claim7, wherein the timing event rule comprises pre-post event rule thatcontrols modification of memory of the each doublet and that depends onthe difference between the timing of events transmitted by thepresynaptic unit and the timing of at least one subsequent eventtransmitted by the postsynaptic unit.
 9. The system of claim 7, whereinthe timing event rule comprises post-pre event rule that controlsmodification of memory of the each doublet and that depends on thedifference between the timing of events transmitted by the presynapticunit and the timing of at least one preceding pulse transmitted by thepostsynaptic unit.
 10. The system of claim 5, wherein each doublet isconfigured to update its memory according to a predefined post eventrule that is triggered by its corresponding postsynaptic unit.
 11. Thesystem of claim 10, wherein the post event rule depends on thedifference between the timing of pulse of the postsynaptic unit and thetiming of at least one preceding pulse of the presynaptic unit.
 12. Thesystem of claim 1, wherein the memory of each unit is updated by atomicaddition.
 13. The system of claim 1, wherein the neuronal networkfurther comprises a plurality of triplets each having a memory, eachtriplet being configured to access the memory of two of the plurality ofunits, wherein each triplet is operable to update its own triplet memoryand the memory at least one of the two units in accordance with atriplet rule, wherein execution of triplet update rules for theplurality of triplets is order-independent.
 14. The system of claim 13,wherein the neuronal network is represented as a directed graph.
 15. Thesystem of claim 14, wherein the representation of a neuronal network ismapped to the interconnected plurality of units independently of thephysical and electrical structure of the units, the doublets and thetriplets.
 16. The system of claim 15, wherein the neuronal network isexpressed in a specification provided in non-transitory storage andcoded according to a hardware description language.
 17. The system ofclaim 16, wherein the specification is operable to reconfigure asemiconductor integrated circuit.
 18. A method of implementing neuronalnetworks embodied in one or more integrated circuits, the methodcomprising: interconnecting a plurality of units embodied in one or moreintegrated circuits using doublets configured to modify a memory of apostsynaptic unit responsive to an event received from a presynapticunit; configuring doublet event rules that determine how the doubletsrespond to events; and configuring a unit update rule for each unit thatcontrols the response of the each unit to memory updates initiated by adoublet, wherein execution of the doublet event rules isorder-independent and execution of the unit update rules isorder-independent; wherein configuring doublet event rules includesconfiguring each of the doublet event rules to be executed within a timestep having a duration determined by a system clock after receiving anevent during the time step.
 19. The method of claim 18, wherein eachpresynaptic unit maintains an event condition that controls transmissionof events to a doublet.
 20. The method of claim 18, further comprisingconfiguring an after-event unit update rule for each presynaptic unit tobe executed in association with the transmission of the events, whereinthe after-event unit update rule causes modification of memory of theeach presynaptic unit.
 21. The method of claim 18, wherein each doubletmodifies the memory of the postsynaptic unit memory by atomic addition.22. The method of claim 18, wherein the doublet event rule for eachdoublet includes a timing event rule that controls modification of amemory of the each doublet based on timing of pulses associated with oneor more of the plurality of units.
 23. The method of claim 22, whereinthe timing event rule comprises pre-post event rule that controlsmodification of memory of the each doublet and that depends on thedifference between the timing of pulses of a presynaptic unit and thetiming of pulses of at least one subsequent pulse of the postsynapticunit.
 24. The method of claim 22, wherein the timing event rulecomprises post-pre event rule that controls modification of memory ofthe each doublet and that depends on the difference between the timingof pulses of the presynaptic unit and the timing of pulses of at leastone preceding pulse of the postsynaptic unit.
 25. The method of claim22, wherein execution of the doublet event rule for each doublet istriggered by an event received from a presynaptic unit.
 26. The methodof claim 18, further comprising interconnecting a second plurality ofunits using triplets configured to access memory of a pair oftriplet-connected units; and configuring a triplet update rule for eachtriplets that controls updates to the memory of the each triplets andthe memory of at least one of its corresponding pair oftriplet-connected units, wherein execution of triplet update rules isorder-independent.
 27. The method of claim 26, wherein the update rulefor each triplet responds to information maintained in memories of thepair of units connected by the each triplet.
 28. The method of claim 26,wherein triplets update memories of units by atomic addition.
 29. Themethod of claim 26, wherein each step of interconnecting pluralities ofunits, and each step of configuring rules are performed in accordancewith a representation of a desired neuronal network.
 30. The method ofclaim 29, wherein the desired neuronal network is represented as adirected graph.
 31. The method of claim 29, wherein the representationof a neuronal network is mapped to the interconnected plurality of unitsindependently of: the physical and electrical structure of the pluralityof units; the physical and electrical structure of doublets used toconnect the plurality of units; and of the physical and electricalstructure of the triplets used to the plurality of units.
 32. The methodof claim 29, wherein the pluralities of units, the doublets and thetriplets are embodied in a semiconductor integrated circuit.
 33. Themethod of claim 32, further comprising expressing the neuronal networkin a specification using a hardware description language.
 34. The methodof claim 33, wherein the specification is operable to reconfigure asemiconductor integrated circuit.
 35. The method of claim 33, whereinthe specification is used to manufacture a semiconductor integratedcircuit.
 36. The method of claim 35, wherein the first number of unitsincludes certain of the second number of units.
 37. The method of claim36, wherein the doublet event rules are executable in parallel, thetriplet update rules are executable in parallel, and the unit updaterules are executable in parallel.
 38. The method of claim 37, whereinthe triplet update rules and the unit update rules are executed oncewithin a time step having a duration determined by a system clock. 39.The method of claim 36, wherein the doublet event rule comprises pulsedelivery rule that modifies postsynaptic unit memory based on thecontent of its associated doublet memory.
 40. The method of claim 36,wherein each doublet is configured to respond to events communicated byits corresponding postsynaptic unit by initiating updates of doubletmemory according to a predefined post event rule configured for the eachdoublet.
 41. The method of claim 40, wherein the post event rule dependson the difference between the timing of pulse of the postsynaptic unitand the timing of at least one preceding pulse of the presynaptic unit.42. A system configured to provide a neuronal network, the systemcomprising: one or more integrated circuits having a neuronal networkembodied therein, the neuronal network comprising: a plurality of units,each unit comprising a non-transitory unit memory that is periodicallyupdated according to a unit update rule associated with the each unit;and a plurality of doublets, each doublet connecting a pair of units,wherein each doublet is configured to respond to a stimulation by one ofthe pair of units by initiating update of the memory of the other unitaccording to a predefined doublet event rule associated with the eachdoublet; wherein updates to unit memories are performed within a periodof a time determined by a system clock; wherein all of the updates arecompleted before the period of time expires; wherein each pair of unitsconnected by a doublet comprises a presynaptic unit and a postsynapticunit; and wherein the connecting doublet is configured to modify thememory of the postsynaptic unit by atomic addition.
 43. The system ofclaim 42, wherein the doublet event rule comprises a pulse delivery rulethat modifies postsynaptic unit memory based on the content of a memoryof the connecting doublet.
 44. The system of claim 42, wherein theexecution of the doublet event rule of the connecting doublet istriggered by an event generated by the presynaptic unit.
 45. The systemof claim 42, wherein the doublet event rules for at least two doubletsare executable in parallel, and wherein the unit update rules for atleast two of the units are executable in parallel.
 46. The system ofclaim 45, wherein the post event rule depends on the difference betweenthe timing of pulse of the postsynaptic unit and the timing of at leastone preceding pulse of the presynaptic unit.
 47. The system of claim 42,wherein, for at least one doublet, there is a delay between stimulationby the one of the pair of units and the initiation of the memory updateof the other unit.
 48. The system of claim 42, wherein each unit of theplurality of units is configured to generate an event based on contentof memory of the each unit, and wherein each unit is further configuredto communicate the event to a doublet connected to the each unit. 49.The system of claim 48, wherein an after-event unit update rule isconfigured for each of the plurality of units that is executed after theevent has been generated, wherein the after-event unit update rulemodifies memory of the each unit.
 50. The system of claim 42, whereineach doublet comprises a memory and wherein the doublet event rule foreach doublet includes a timing event rule that controls modification ofa memory of the each doublet based on timing of events associated withone or more of the plurality of units.
 51. The system of claim 50,wherein the timing event rule comprises pre-post event rule thatcontrols modification of memory of the doublet and that depends on thedifference between the timing of pulses of the presynaptic unit and thetiming of pulses of at least one subsequent pulse of the postsynapticunit.
 52. The system of claim 50, wherein the timing event rulecomprises post-pre event rule that controls modification of memory ofthe doublet and that depends on the difference between the timing ofpulses of the presynaptic unit and the timing of pulses of at least onepreceding pulse of the postsynaptic unit.
 53. The system of claim 42,wherein the neuronal network further comprises a plurality of triplets,each triplet configured to access the memory of two of the units,wherein each triplet is configured to initiate updates of the memory ofat least one of the two units according to a triplet update ruleassociated with the each triplet.
 54. The system of claim 53, whereinone or more of the plurality of units is connected to both a doublet anda triplet.
 55. The system of claim 53, wherein at least one of the unitshas a triplet update rule that is executable in parallel with thetriplet update rule of another unit.
 56. The system of claim 53, whereineach pair of units connected by a triplet comprises a presynaptic unitand a postsynaptic unit, wherein the connecting triplet is configured tomodify the memory of at least one of the presynaptic unit and thepostsynaptic unit by atomic addition.
 57. The system of claim 56,wherein the triplet update rule for the connecting triplet operatesbased on information maintained in the memories of the presynaptic unitand the postsynaptic unit.
 58. The system of claim 57, wherein thetriplet update rule for the connecting triplet is configured to causemodification of a memory of the connecting triplet.
 59. The system ofclaim 57, wherein the connecting triplet is configured to modify thememories of one or more of the presynaptic and postsynaptic units byatomic addition.
 60. The system of claim 53, wherein the neuronalnetwork is represented as a directed graph.
 61. The system of claim 60,wherein the representation of a neuronal network is mapped to theinterconnected plurality of units independently of the physical andelectrical structure of the units, the doublets and the triplets. 62.The system of claim 61, wherein the neuronal network is expressed in aspecification provided in non-transitory storage and coded according toa hardware description language.
 63. The system of claim 62, wherein thespecification is operable to reconfigure a semiconductor integratedcircuit.
 64. The system of claim 62, wherein the specification controlsmanufacture of a semiconductor integrated circuit.
 65. The system ofclaim 61, wherein the neuronal network is expressed in a specificationprovided in non-transitory storage and coded in a programming language.66. The system of claim 42, wherein each doublet is configured torespond by initiating update of doublet memory according to a predefinedpost event rule associated with the each doublet triggered by an eventcommunicated by the postsynaptic unit.
 67. The system of claim 42,wherein the events emulate pulses of excitable neurons.